參數(shù)資料
型號(hào): AM29F010A-55
廠商: Advanced Micro Devices, Inc.
英文描述: LM120/LM320 Series 3-Terminal Negative Regulators; Package: TO-220; No of Pins: 3; Qty per Container: 45; Container: Rail
中文描述: 1兆位(128畝× 8位)的CMOS 5.0伏只,統(tǒng)一部門(mén)快閃記憶體
文件頁(yè)數(shù): 16/31頁(yè)
文件大?。?/td> 389K
代理商: AM29F010A-55
16
Am29F010A
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.”
Only an erase operation can change
a “0” back to a “1.”
Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys-
tem can guarantee that the time between additional
sector erase commands will always be less than 50
μ
s.
section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands are ignored until the
erase operation is complete. If DQ3 is “0”, the device
will accept additional sector erase commands. To en-
sure the command has been accepted, the system
software should check the status of DQ3 prior to and
following each subsequent sector erase command. If
DQ3 is high on the second status check, the last com-
mand might not have been accepted. Table 5 shows
the outputs for DQ3.
Table 5.
Write Operation Status
Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2.
DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
Embedded Erase Algorithm
0
Toggle
0
1
Erase
Suspend
Mode
Reading within Erase Suspended Sector
1
No toggle
0
N/A
Reading within Non-Erase Suspended Sector
Data
Data
Data
Data
相關(guān)PDF資料
PDF描述
AM29F010A LM120/LM320 Series 3-Terminal Negative Regulators; Package: TO-3; No of Pins: 2; Qty per Container: 50; Container: Tray
AM29F010A-120 LM120/LM320 Series 3-Terminal Negative Regulators; Package: TO-3; No of Pins: 2; Qty per Container: 50; Container: Tray
AM29F010A-45 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
AM29F010A-70 LM120/LM320 Series 3-Terminal Negative Regulators; Package: TO-220; No of Pins: 3; Qty per Container: 45; Container: Rail
AM29F010A-90 LM120/LM320 Series 3-Terminal Negative Regulators; Package: TO-220; No of Pins: 3; Qty per Container: 45; Container: Rail
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