參數資料
    型號: Am29F200AT-90SIB
    廠商: Advanced Micro Devices, Inc.
    英文描述: 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    中文描述: 2兆位(256畝x 8-Bit/128畝x 16位),5.0伏的CMOS只,引導扇區(qū)閃存
    文件頁數: 8/39頁
    文件大?。?/td> 237K
    代理商: AM29F200AT-90SIB
    8
    Am29F200A
    P R E L I M I N A R Y
    DEVICE BUS OPERATIONS
    This section describes the requirements and use of the
    device bus operations, which are initiated through the
    internal command register. The command register itself
    does not occupy any addressable memory location.
    The register is composed of latches that store the com-
    mands, along with the address and data information
    needed to execute the command. The contents of the
    register serve as inputs to the internal state machine.
    The state machine outputs dictate the function of the
    device. The appropriate device bus operations table
    lists the inputs and control levels required, and the re-
    sulting output. The following subsections describe
    each of these operations in further detail.
    Table 1.
    Am29F200A Device Bus Operations
    Legend:
    L = Logic Low = V
    IL
    , H = Logic High = V
    IH
    , V
    ID
    = 12.0
    ±
    0.5 V, X = Don’t Care, D
    IN
    = Data In, D
    OUT
    = Data Out, A
    IN
    = Address In
    Note:
    See the sections on Sector Protection and Temporary Sector Unprotect for more information.
    Word/Byte Configuration
    The BYTE# pin controls whether the device data I/O
    pins DQ15–DQ0 operate in the byte or word configura-
    tion. If the BYTE# pin is set at logic ‘1’, the device is in
    word configuration, DQ15–DQ0 are active and con-
    trolled by CE# and OE#.
    If the BYTE# pin is set at logic ‘0’, the device is in byte
    configuration, and only data I/O pins DQ0–DQ7 are ac-
    tive and controlled by CE# and OE#. The data I/O pins
    DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
    an input for the LSB (A-1) address function.
    Requirements for Reading Array Data
    To read array data from the outputs, the system must
    drive the CE# and OE# pins to V
    IL
    . CE# is the power
    control and selects the device. OE# is the output control
    and gates array data to the output pins. WE# should re-
    main at V
    IH
    . On x16 (word-wide) devices, the BYTE# pin
    determines whether the device outputs array data in
    words or bytes.
    The internal state machine is set for reading array
    data upon device power-up, or after a hardware re-
    set. This ensures that no spurious alteration of the
    memory content occurs during the power transition.
    No command is necessary in this mode to obtain
    array data. Standard microprocessor read cycles that
    assert valid addresses on the device address inputs
    produce valid data on the device data outputs. The
    device remains enabled for read access until the
    command register contents are altered.
    See “Reading Array Data” for more information. Refer
    to the AC Read Operations table for timing specifica-
    tions and to the Read Operations Timings diagram for
    the timing waveforms. I
    CC1
    in the DC Characteristics
    table represents the active current specification for
    reading array data.
    Writing Commands/Command Sequences
    To write a command or command sequence (which in-
    cludes programming data to the device and erasing
    sectors of memory), the system must drive WE# and
    CE# to V
    IL
    , and OE# to V
    IH
    .
    On x16 (word-wide) devices, for program operations,
    the BYTE# pin determines whether the device ac-
    cepts program data in bytes or words. Refer to
    “Word/Byte Configuration” for more information.
    Operation
    CE#
    OE#
    WE#
    RESET#
    A0–A16
    DQ0–DQ7
    DQ8–DQ15
    BYTE#
    = V
    IH
    BYTE#
    = V
    IL
    Read
    L
    L
    H
    H
    A
    IN
    D
    OUT
    D
    OUT
    High-Z
    Write
    L
    H
    L
    H
    A
    IN
    D
    IN
    D
    IN
    High-Z
    CMOS Standby
    V
    CC
    ± 0.5 V
    X
    X
    V
    CC
    ± 0.5 V
    X
    High-Z
    High-Z
    High-Z
    TTL Standby
    H
    X
    X
    H
    X
    High-Z
    High-Z
    High-Z
    Output Disable
    L
    H
    H
    H
    X
    High-Z
    High-Z
    High-Z
    Hardware Reset
    X
    X
    X
    L
    X
    High-Z
    High-Z
    High-Z
    Temporary Sector Unprotect
    (See Note)
    X
    X
    X
    V
    ID
    A
    IN
    D
    IN
    D
    IN
    X
    相關PDF資料
    PDF描述
    AM29F200AB-120FC 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    Am29F200AB-120FCB 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    AM29F200AB-120FE 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    AM29F200AB-120FEB 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    Am29F200AB-120FIB 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory
    相關代理商/技術參數
    參數描述
    AM29F200BB-120EC 制造商:Advanced Micro Devices 功能描述:
    AM29F200BB-120SI 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 120ns 44-Pin SOIC
    AM29F200BB-120SI\T 制造商:Spansion 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 120ns 44-Pin SOIC T/R
    AM29F200BB-45SI 制造商:Advanced Micro Devices 功能描述:
    AM29F200BB-55EF 功能描述:閃存 2M (256KX8/128KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel