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參數(shù)資料
| 型號： | AM29F200BB-45 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 2兆位（256畝x 8-Bit/128畝x 16位），5.0伏的CMOS只，引導扇區(qū)閃存 |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AM29F200BB-45 |
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Am29F200B
GENERAL DESCRIPTION
The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The 8 bits of data appear on DQ0–DQ7; the 16 bits on
DQ0–DQ15. The Am29F200B is offered in 44-pin SO
and 48-pin TSOP packages. The device is also avail-
able in Known Good Die (KGD) form. For more
information, refer to publication number 21257. This
device is designed to be programmed in-system with
the standard system 5.0 volt V
CC
supply. A 12.0 volt
V
PP
is not required for program or erase operations.
The device can also be reprogrammed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.32 μm
process technology, and offers all the features and
benefits of the Am29F200A, which was manufactured
using 0.5 μm process technology.
The standard device offers access times of 45, 50, 55,
70, 90, and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle)
status bits
. After a program or erase
cycle has been completed, the device is ready to read
array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby
mode
. Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am29F400AT-120EIB | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| Am29F400AT-65EIB | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F400AT-70EC | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F400AB-65FI | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F400AT | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F200BB-45SI | 制造商:Advanced Micro Devices 功能描述: |
| AM29F200BB-55EF | 功能描述:閃存 2M (256KX8/128KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AM29F200BB-55EF\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 55ns 48-Pin TSOP T/R |
| AM29F200BB-70EC | 制造商:Spansion 功能描述:IC, FLASH MEM, 2MBIT, 70NS, 48-TSOP, Memory Type:Flash - NOR, Memory Size:2Mbit, |
| AM29F200BB-70ED | 制造商:Spansion 功能描述:IC 2MEG FLSH 256KX16 BOTTOM SE 制造商:Spansion 功能描述:IC, FLASH MEM, 2MBIT, 70NS, 48-TSOP, Memory Type:Flash - NOR, Memory Size:2Mbit, |
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