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參數(shù)資料
| 型號： | AM29F200BB-55 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 2兆位（256畝x 8-Bit/128畝x 16位），5.0伏的CMOS只，引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 118K |
| 代理商： | AM29F200BB-55 |
2
Am29F200A Known Good Die
1/13/98
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29F200A in Known Good Die (KGD) form is a
2 Mbit, 5.0 Volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same reli-
ability and quality as AMD products in packaged form.
Am29F200A Features
The Am29F200A is organized as 262,144 bytes of 8
bits each or 131,072 words of 16 bits each. The 8-bit
data appears on DQ0-DQ7; the 16-bit data appears on
DQ0-DQ15. This device is designed to be programmed
in-system with the standard system 5.0 Volt V
CC
sup-
ply. A 12.0 volt V
PP
is not required for program or erase
operations.
The standard Am29F200A in KGD form offers an ac-
cess time of 90 or 120 ns, allowing high-speed micro-
processors to operate without wait states. To eliminate
bus contention the device has separate chip enable
(CE#), write enable (WE#), and output enable (OE#)
controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6/
DQ2 (toggle)
status bits
. After a program or erase
cycle has been completed, the device is ready to read
array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby mode
.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash mem-
ory manufacturing experience to produce the highest lev-
els of quality, reliability and cost effectiveness. The device
electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F200A data sheet, publication
number 20380, for full electrical specifications on the
Am29F200A.
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F200A KGD
Speed Option (V
CC
= 5.0 V
±
10%)
-90
-120
Max access time, ns (t
ACC
)
90
120
Max CE# access time, ns (t
CE
)
90
120
Max OE# access time, ns (t
OE
)
35
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F200BB-70 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F200BB-90 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F200BT-120 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F200BT-90 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| AM29F200A-1 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Sectored Flash Memory-Die Revision 1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F200BB-55EF | 功能描述:閃存 2M (256KX8/128KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AM29F200BB-55EF\T | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 55ns 48-Pin TSOP T/R |
| AM29F200BB-70EC | 制造商:Spansion 功能描述:IC, FLASH MEM, 2MBIT, 70NS, 48-TSOP, Memory Type:Flash - NOR, Memory Size:2Mbit, |
| AM29F200BB-70ED | 制造商:Spansion 功能描述:IC 2MEG FLSH 256KX16 BOTTOM SE 制造商:Spansion 功能描述:IC, FLASH MEM, 2MBIT, 70NS, 48-TSOP, Memory Type:Flash - NOR, Memory Size:2Mbit, |
| AM29F200BB70EE | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 70ns 48-Pin TSOP |
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