參數(shù)資料
型號(hào)： AM29F200BB-90EC
廠商： SPANSION LLC
元件分類： PROM
英文描述： Flash Memory IC; Access Time, Tacc:90ns; Package/Case:48-TSOP; Leaded Process Compatible:No; Memory Configuration:256K x 8; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V; Mounting Type:Surface Mount RoHS Compliant: No
中文描述： 128K X 16 FLASH 5V PROM, 90 ns, PDSO48
封裝： MO-142DD, TSOP-48
文件頁數(shù)： 3/41頁
文件大小： 818K
代理商： AM29F200BB-90EC
March 3, 2009 21526D5
Am29F200B
9
D A TA
SH EE T
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section in the appropriate data sheet for timing
diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
相關(guān)PDF資料
PDF描述
AM29F200BB-90ED Flash Memory IC; Memory Size:2Mbit; Memory Configuration:256K x 8; Package/Case:48-TSOP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Mounting Type:Surface Mount RoHS Compliant: Yes
AM29F200BB-90EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
AM29F200BB-90SD Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
AM29F200BT-120EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes
AM29F200BT-70EC Flash Memory IC; Access Time, Tacc:70ns; Package/Case:48-TSOP; Leaded Process Compatible:No; Memory Configuration:256K x 8; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V; Mounting Type:Surface Mount RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29F200BB-90EF 制造商:Advanced Micro Devices 功能描述:
AM29F200BB-90EI 制造商:Spansion 功能描述:2M CMOS FLASH 5V 制造商:Advanced Micro Devices 功能描述:
AM29F200BB-90SE 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 90ns 44-Pin SOIC
AM29F200BT-120EI 制造商:Advanced Micro Devices 功能描述:256K X 8 FLASH 5V PROM, 120 ns, PDSO48
AM29F200BT-50EE 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 50ns 48-Pin TSOP
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