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參數(shù)資料
| 型號： | Am29F400AT-65FIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| 中文描述： | 4兆位（524,288 x 8-Bit/262，144 x 16位），5.0伏的CMOS只，扇區(qū)擦除閃存 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 136K |
| 代理商： | AM29F400AT-65FIB |
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Am29F400AT/Am29F400AB
13
P R E L I M I N A R Y
5
Autoselect Command
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As
such, manufacture and device codes must
be accessible while the device resides in the target
system. PROM programmers typically access the sig-
nature codes by raising A9 to a high voltage. However,
multiplexing high voltage onto the address lines is not
generally a desirable system design practice.
The device contains an autoselect command operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the autose-
lect command sequence into the command register.
Following the command write, a read cycle from ad-
dress XX00H retrieves the manufacture code of 01H. A
read cycle from address XX01H returns the device
code (Am29F400AT = 23H and Am29F400AB = ABH
for x8 mode; Am29F400AT = 2223H and Am29F400AB
= 22ABH for x16 mode) (see Tables 3 and 4).
All manufacturer and device codes will exhibit odd par-
ity with DQ7 defined as the parity bit.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0)
= (0, 1, 0) will produce a logical “1” at device output
DQ0 for a protected sector.
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
Byte/Word Programming
The device is programmed on a byte-by-byte (or
word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These
are followed by the program setup command and data
write cycles. Addresses are latched on the falling edge
of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever hap-
pens first. The rising edge of CE or WE (whichever hap-
pens first) begins programming using the Embedded
Program Algorithm. Upon executing the algorithm, the
system is notrequired to provide further controls or tim-
ings. The device will automatically provide adequate in-
ternally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed
when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time
the device returns to the read mode and addresses are
no longer latched (see Table 8, Write Operation Sta-
tus). Therefore, the device requires that a valid address
to the device be supplied by the system at this particu-
lar instance of time for Data Polling operations. Data
Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the
data at that particular location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm but a read from reset/read
mode will show that the data is still “013”. Only erase
operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Programming Algo-
rithm using typical command strings and
bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Chip erase does notrequire the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
erase is performed sequentially on all sectors at the
same time (see Table “Erase and Programming Perfor-
mance”). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the device returns to read
the mode.
Figure 1 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command. The sector
address (any address location within the
desired sector) is latched on the falling edge of WE,
while the command (30H) is latched on the rising edge
of WE. After a time-out of 100
μ
s from the rising edge
of the last sector erase command, the sector erase op-
eration will begin.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
sequentially erased. The time between writes must be
less than 100
μ
s otherwise that command will not be
相關(guān)PDF資料 |
PDF描述 |
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| AM29F400BB-90DGE1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| AM29F400B-1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| Am29F400BT-75DTC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| Am29F400BB-75DTC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
| AM29F400BT-75DTC1 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory-Die Revision 1 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F400AT-90SC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 256K x 16, 44 Pin, Plastic, SOP |
| AM29F400BB | 制造商: 功能描述: 制造商:undefined 功能描述: |
| AM29F400BB120EC | 制造商:AMD 功能描述:New |
| AM29F400BB-120SC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F400BB120SI | 制造商:AMD 功能描述:* |
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