參數資料
型號： AM29F400BB-90SF
廠商： SPANSION LLC
元件分類： PROM
英文描述： Flash Memory IC; Memory Size:4Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
中文描述： 256K X 16 FLASH 5V PROM, 90 ns, PDSO44
封裝： LEAD FREE, MO-180AAA, SOP-44
文件頁數： 8/43頁
文件大?。?/td> 856K
代理商： AM29F400BB-90SF
14
Am29F400B
21505E8 November 11, 2009
D A TA
SH EE T
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “The Erase Resume
mode.” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
m i ng op erat io n. Th e Byt e Pr ogra m co mm an d
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note:
See Table 5 for program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any comm ands wr it ten to th e chip dur ing th e
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “The
Suspend mode.” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the “Erase/Program Operations” tables in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關PDF資料
PDF描述
AM29F400BT-55EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29
AM29F400BT-55SF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes
AM29F400BT-70EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes
AM29F400BT-70SF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes
AM29F400BT-90EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes
相關代理商/技術參數
參數描述
AM29F400BB-90SF 制造商:Spansion 功能描述:FLASH MEMORY IC
AM29F400BB-90SF\T 功能描述:閃存 4M (512KX8/256Kx16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel
AM29F400BB-90SI 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K/256K x 8bit/16bit 90ns 44-Pin SO
AM29F400BT-150EI 制造商:Spansion 功能描述:4M (512KX8/256KX16) 5V, BOOT BLOCK, TOP, TSOP48, IND - Trays
AM29F400BT-45EF 制造商:Spansion 功能描述:NOR Flash Parallel 5V 4Mbit 512K/256K x 8bit/16bit 45ns 48-Pin TSOP 制造商:Spansion 功能描述:FLASH PARALLEL 5V 4MBIT 512KX8/256KX16 45NS 48TSOP - Trays
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