參數(shù)資料
型號: AM29F400BT-70EC
廠商: SPANSION LLC
元件分類: PROM
英文描述: Flash Memory IC; Access Time, Tacc:70ns; Package/Case:48-TSOP; Leaded Process Compatible:No; Memory Configuration:256K x 16 / 512K x 8; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V; Mounting Type:Surface Mount RoHS Compliant: No
中文描述: 256K X 16 FLASH 5V PROM, 70 ns, PDSO48
封裝: MO-142DD, TSOP-48
文件頁數(shù): 9/43頁
文件大?。?/td> 865K
代理商: AM29F400BT-70EC
March 3, 2009 21505E6
Am29F400B
15
D A TA
SH EE T
s, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 s, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to “The Erase Resume command is
mation on these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the “Erase/Program Operations” tables in
the “AC Characteristics” section for parameters, and to
Figure 14 for timing diagrams.
相關(guān)PDF資料
PDF描述
AM29F400BT-70ED Flash Memory IC; Memory Configuration:256K x 16 / 512K x 8; Package/Case:48-TSOP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5.5V; Access Time, Tacc:70ns; Mounting Type:Surface Mount RoHS Compliant: Yes
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AM29F400BB-55EF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes
AM29F400BB-55SF Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes
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