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參數(shù)資料
| 型號： | Am29F800BB-120DTI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Dual Retriggerable Monostable Multivibrators 16-TSSOP -40 to 85 |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），5.0伏的CMOS只，引導(dǎo)扇區(qū)快閃記憶體模修訂1 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 207K |
| 代理商： | AM29F800BB-120DTI |
2
Am29F800B Known Good Die
5/4/98
SU PP L E ME NT
GENERAL DESCRIPTION
The Am29F800B in Known Good Die (KGD) form is a
8 Mbit, 5.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same relia-
bility and quality as AMD products in packaged form.
Am29F800B Features
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
w o rd s . Th e w o r d -w ide da ta (x 1 6 ) a ppe ars o n
DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed
in-system with the standard system 5.0 volt VCC
supply. A 12.0 V VPP is not required for write or erase
operations. The device can also be programmed in
standard EPROM programmers.
This device is manufactured using AMD’s 0.35 m
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 m process technology.
To eliminate bus contention the device has separate
chip enable (CE#), write enable (WE#) and output
enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i gh es t leve l s of q ual ity, re lia bil i ty an d c o s t
effectiveness. The device electrically erases all
bi t s w i thin a s e c t or s i multaneous ly v i a
F o w l e r -N ordheim t unneling. T h e data is
programmed using hot electron injection.
ELECTRICAL SPECIFICATIONS
Refer to the Am29F800B data sheet, PID 21504, for full
electrical specifications on the Am29F800B in KGD
form.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am29F800BB-120DWE | Dual Retriggerable Monostable Multivibrators 16-TSSOP -40 to 85 |
| Am29F800BB-120DWI | Dual Retriggerable Monostable Multivibrators 16-TSSOP -40 to 85 |
| AM29F800BB-120DWE1 | Dual Retriggerable Monostable Multivibrators 16-TSSOP -40 to 85 |
| Am29F800BB-120ECB | Dual Retriggerable Monostable Multivibrators 16-VQFN -40 to 85 |
| AM29F800BB-120EC | Flash Memory IC; Access Time, Tacc:120ns; Memory Configuration:512K x 16 / 1M x 8; Memory Size:8Mbit; Supply Voltage Max:5.5V; Mounting Type:Surface Mount |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F800BB120SC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F800BB-55EC | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M/512K x 8bit/16bit 55ns 48-Pin TSOP |
| AM29F800BB-55EF | 功能描述:閃存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AM29F800BB-55EF\\T | 制造商:Spansion 功能描述:IC 8MEG(512K16)BOTTOM SCTOR 100K (CS39S) |
| AM29F800BB-55EF\T | 功能描述:閃存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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