參數(shù)資料
型號： AM29F800BB-120EF
廠商： SPANSION LLC
元件分類： PROM
英文描述： Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes
中文描述： 512K X 16 FLASH 5V PROM, 120 ns, PDSO48
封裝： LEAD FREE, MO-142DD, TSOP-48
文件頁數(shù)： 3/45頁
文件大?。?/td> 1402K
代理商： AM29F800BB-120EF
March 3, 2009 21504E6
Am29F800B
9
D A TA SH EE T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29F800B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
Operation
CE#
OE#
WE#
RESET#
A0–A18
DQ0–DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
H
AIN
DOUT
High-Z
Write
L
H
L
H
AIN
DIN
High-Z
CMOS Standby
VCC ± 0.5 V
X
VCC ± 0.5 V
X
High-Z
TTL Standby
H
X
H
X
High-Z
Output Disable
L
H
X
High-Z
Hardware Reset
X
L
X
High-Z
Temporary Sector Unprotect
(See Note)
X
VID
AIN
DIN
X
相關(guān)PDF資料
PDF描述
AM29F800BB-120SD Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes
AM29F800BB-55ED Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes
AM29F800BB-70EC Flash Memory IC; Access Time, Tacc:70ns; Package/Case:48-TSOP; Leaded Process Compatible:No; Memory Configuration:512K x 16 / 1M x 8; Memory Size:8Mbit; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V RoHS Compliant: No
AM29F800BB-70ED Flash Memory IC; Memory Size:8Mbit; Memory Configuration:512K x 16 / 1M x 8; Package/Case:48-TSOP; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns RoHS Compliant: Yes
AM29F800BB-70SD Flash Memory IC; Memory Size:8Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM29F800BB120SC 制造商:Advanced Micro Devices 功能描述:
AM29F800BB-55EC 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M/512K x 8bit/16bit 55ns 48-Pin TSOP
AM29F800BB-55EF 功能描述:閃存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
AM29F800BB-55EF\\T 制造商:Spansion 功能描述:IC 8MEG(512K16)BOTTOM SCTOR 100K (CS39S)
AM29F800BB-55EF\T 功能描述:閃存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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