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參數(shù)資料
| 型號： | AM29LL800B |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | DSUB 13C3 FLOA DI |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），2.2伏的CMOS只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29LL800B |
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Am29LL800B
9
A D V A N C E I N F O R M A T I O N
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory. During power-up, the
system must ensure that RESET# is high t
RSTW
before
asserting a valid address (see Figure 1 and the
Erase/Program Operations table).
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
READY
(not during Embed-
ded Algorithms). The system can read data t
RH
after
the RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Figure 1.
Power-up and Reset Timings
RESET#
V
CC
Address
Data
2.2 – 2.7 V
VALID
t
CE
t
ACC
0 V
VALID OUTPUT
t
RSTW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LL800BB-150EC | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| Am29LL800BB-150ECB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| AM29LL800BB-150EI | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| Am29LL800BB-150EIB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
| AM29LL800BB-150FC | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 2.2 Volt-only Boot Sector Flash Memory |
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