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參數(shù)資料
| 型號(hào)： | AM29LV001BB-5JK |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 1兆位（128畝× 8位）的CMOS 3.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 493K |
| 代理商： | AM29LV001BB-5JK |
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May 5, 2006 21557F4
Am29LV001B
7
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device.
Table 1
lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1.
Am29LV001B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0 ± 0.5 V, X = Don’t Care, A
IN
= Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A16–A0.
2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by
using programming equipment. See “
“Sector Protection/Unprotection” on page 10
” .
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See
“Reading Array Data” on page 13
for more infor-
mation. Refer to the AC
“Read Operations” on page 26
table for timing specifications and to
Figure 13, on page
26
for the timing diagram. I
CC1
in the DC Characteris-
tics table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The
“Byte
Program Command Sequence” on page 13
section
contains details on programming data to the device
using both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 2 on page 9
indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The
“Command Definitions”
on page 13
section contains details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
Operation
CE#
L
L
OE#
L
H
X
H
X
WE#
H
L
X
H
X
RESET#
H
H
V
CC
±
0.3 V
H
L
Addresses (Note 1)
A
IN
A
IN
X
X
X
Sector Address, A6 =
L, A1 = H, A0 = L
Sector Address, A6 =
H, A1 = H, A0 = L
DQ0–DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
Read
Write
Standby
Output Disable
Reset
V
CC
±
0.3 V
L
X
Sector Protect (Note 2)
L
H
L
V
ID
D
IN
, D
OUT
Sector Unprotect (Note 2)
L
H
L
V
ID
D
IN
, D
OUT
Temporary Sector
Unprotect
X
X
X
V
ID
A
IN
D
IN
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