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參數(shù)資料
| 型號： | AM29LV001BB-70JF |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 1兆位（128畝× 8位）的CMOS 3.0伏，只引導扇區(qū)閃存 |
| 文件頁數(shù)： | 10/43頁 |
| 文件大小： | 493K |
| 代理商： | AM29LV001BB-70JF |
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8
Am29LV001B
21557F4 May 5, 2006
D A T A S H E E T
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to
“Autoselect Mode” on page 9
and
“Autoselect Command Sequence” on page 13
for more
information.
I
CC2
in the DC Characteristics table represents the
active current specification for the write mode. The
“AC
Characteristics” on page 26
section contains timing
specification tables and timing diagrams for write
operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to
“Write Operation
Status” on page 18
for more information, and to
“AC
Characteristics” on page 26
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current is greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC5
in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.The system may use the
RESET# pin to force the device into the standby mode.
Refer to
“Standby Mode” on page 8
for more
information.
Refer to the AC Characteristics tables for RESET#
parameters and to
Figure 14, on page 27
for the timing
diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
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