參數(shù)資料
型號: AM29LV001BT-70JF
廠商: Advanced Micro Devices, Inc.
英文描述: 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述: 1兆位(128畝× 8位)的CMOS 3.0伏,只引導(dǎo)扇區(qū)閃存
文件頁數(shù): 16/43頁
文件大小: 493K
代理商: AM29LV001BT-70JF
14
Am29LV001B
21557F4 May 5, 2006
D A T A S H E E T
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See
“Write Operation Status” on page 18
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
“0” back to a “1”. Attempting to do so may halt the oper-
ation and set DQ5 to “1,” or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read shows that the data is still
“0”. Only erase operations can convert a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time.
Table 5 on page 17
shows the requirements
for the command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares for both cycles. The device then returns
to reading array data.
Figure 3
illustrates the algorithm for the program oper-
ation. See the table
“Erase/Program Operations” on
page 28
for parameters, and
Figure 15, on page 29
for
timing diagrams.
Note:
See
Table 5 on page 17
for program command
sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
Table 5 on
page 17
shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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