- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366453 > AM29LV004BB-120FC (ADVANCED MICRO DEVICES INC) 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory PDF資料下載
參數(shù)資料
| 型號： | AM29LV004BB-120FC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 512K X 8 FLASH 3V PROM, 120 ns, PDSO40 |
| 封裝： | REVERSE, MO-142CD, TSOP-40 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 769K |
| 代理商： | AM29LV004BB-120FC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Am29LV004B
13
Figure 2.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not
accept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defines the valid register command
sequences. Writing
incorrect
address and data
values
or writing them in the
improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must
issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV004BB-120FE | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV004BB-120FI | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV004BT-120EC | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV004BT-120EE | Slide DIP switches are available in 2 through 12 positions and vertical/right angle options |
| AM29LV004BT-120EI | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| am29lv004bt-120ed | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV004BT-90EI | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV008BB-120ECT | 制造商:Spansion 功能描述:IC 8MEG X8, 3 V FLASH BOTTOM B |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:IC SM FLASH 3V 8MB |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:FLASH MEMORY IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。