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參數(shù)資料
| 型號： | AM29LV008BB-90ED |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | Flash Memory IC; Interface Type:Parallel; Memory Size:8Mbit; Memory Configuration:1M x 8; Package/Case:40-TSOP; Supply Voltage:3V; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3.6V RoHS Compliant: Yes |
| 中文描述： | 1M X 8 FLASH 3V PROM, 90 ns, PDSO40 |
| 封裝： | LEAD FREE, MO-142BCD, TSOP-40 |
| 文件頁數(shù)： | 8/41頁 |
| 文件大?。?/td> | 738K |
| 代理商： | AM29LV008BB-90ED |
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Am29LV008B
21524D7 February 24, 2009
D A TA SH EET
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
m i ng op erat io n. Th e Byt e Pr ogra m co mm an d
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The Command Definitions table shows the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t care for both cycles. The device then returns
to reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and Figure 15 for
timing diagrams.
Note: See Table 5 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any comm ands wr it ten to th e chip dur ing th e
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV008BB-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV008BT-120ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV008BT-70RED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV008BT-70REF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV008BT-90ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV008BT-120EC | 制造商:ADV-MICRO-DEV 功能描述: |
| AM29LV008BT-80EC | 制造商:Spansion 功能描述:IC 8 MEG X 8, 3 V FLASH TOP B - Bulk |
| AM29LV008DT-90EC | 制造商:Spansion 功能描述:8M (1MX8) 3V, BOOT BLOCK, TOP, TSOP40, COM - Trays |
| AM29LV010B-45JC | 制造商:Spansion 功能描述:1M (128KX8) 3V, UNIFORM SECTOR, PLCC32, COM - Rail/Tube |
| AM29LV010B-55JCT | 制造商:Spansion 功能描述:1M (128KX8) 3V, UNIFORM SECTOR, PLCC32, COM, T&R - Tape and Reel |
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