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參數(shù)資料
| 型號： | AM29LV008BB120EC |
| 英文描述： | Complete BrainPower Control System Accelerator Verilog Object Code Manual |
| 中文描述： | x8閃存EEPROM的 |
| 文件頁數(shù)： | 31/35頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AM29LV008BB120EC |
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Am29LV040B
31
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2.
Under worst case conditions of 90°C, V
CC
= 2.7 V (3.0 V for -60R), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
15
s
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
11
s
Byte Programming Time
9
300
μs
Excludes system level
overhead (Note 5)
Chip Programming Time
(Note 3)
4.5
13.5
s
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9 and OE#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
7.5
9
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29LV008BB120EE | Single Axis Bundled System Accelerator1 System Manual |
| AM29LV008BB120EI | Complete BrainPower Control System Accelerator Verilog Code Manual |
| AM29LV008BB120FC | IR2171 Current Sense Interface Module Accelerator Verilog Module |
| AM29LV008BB120FE | Slave Motion SPI/Host Register Interface Accelerator Verilog Module |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV008BB-120ECT | 制造商:Spansion 功能描述:IC 8MEG X8, 3 V FLASH BOTTOM B |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:IC SM FLASH 3V 8MB |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:FLASH MEMORY IC |
| AM29LV008BB-80EC | 制造商:Spansion 功能描述:IC 8MEG X8, 3 V FLASH BOTTOM B - Bulk |
| AM29LV008BB-90ED | 制造商:Spansion 功能描述:Flash Memory IC |
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