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  • 參數(shù)資料
    型號: AM29LV033C-120EI
    廠商: ADVANCED MICRO DEVICES INC
    元件分類: PROM
    英文描述: 32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
    中文描述: 4M X 8 FLASH 3V PROM, 120 ns, PDSO40
    封裝: MO-142CD, TSOP-40
    文件頁數(shù): 11/48頁
    文件大?。?/td> 1023K
    代理商: AM29LV033C-120EI
    10
    Am29LV033C
    space that each sector occupies. A “sector address”
    consists of the address bits required to uniquely select
    a sector. The “Command Definitions” section has de-
    tails on erasing a sector or the entire chip, or suspend-
    ing/resuming the erase operation.
    After the system writes the autoselect command se-
    quence, the device enters the autoselect mode. The
    system can then read autoselect codes from the inter-
    nal register (which is separate from the memory array)
    on DQ7–DQ0. Standard read cycle timings apply in
    this mode. Refer to the Autoselect Mode and Autose-
    lect Command Sequence sections for more informa-
    tion.
    I
    CC2
    in the DC Characteristics table represents the ac-
    tive current specification for the write mode. The “AC
    Characteristics” section contains timing specification
    tables and timing diagrams for write operations.
    Accelerated Program Operation
    The device offers accelerated program operations
    through the ACC function. This is one of two functions
    provided by the ACC pin. This function is primarily in-
    tended to allow faster manufacturing throughput at the
    factory.
    If the system asserts V
    HH
    on this pin, the device auto-
    matically enters the aforementioned Unlock Bypass
    mode, temporarily unprotects any protected sectors,
    and uses the higher voltage on the pin to reduce the
    time required for program operations. The system
    would use a two-cycle program command sequence
    as required by the Unlock Bypass mode. Removing
    V
    HH
    from the ACC pin returns the device to normal op-
    eration. Note that the ACC pin must not be at V
    HH
    for
    operations other than accelerated programming, or
    device damage may result.
    Program and Erase Operation Status
    During an erase or program operation, the system
    may check the status of the operation by reading the
    status bits on DQ7–DQ0. Standard read cycle timings
    and I
    CC
    read specifications apply. Refer to “Write Op-
    eration Status” for more information, and to “AC Char-
    acteristics” for timing diagrams.
    Standby Mode
    When the system is not reading or writing to the de-
    vice, it can place the device in the standby mode. In
    this mode, current consumption is greatly reduced,
    and the outputs are placed in the high impedance
    state, independent of the OE# input.
    The device enters the CMOS standby mode when the
    CE# and RESET# pins are both held at V
    CC
    ±
    0.3 V.
    (Note that this is a more restricted voltage range than
    V
    IH
    .) If CE# and RESET# are held at V
    IH
    , but not within
    V
    CC
    ±
    0.3 V, the device will be in the standby mode, but
    the standby current will be greater. The device re-
    quires standard access time (t
    CE
    ) for read access
    when the device is in either of these standby modes,
    before it is ready to read data.
    The device also enters the standby mode when the
    RESET# pin is driven low. Refer to the next section,
    “RESET#: Hardware Reset Pin”.
    If the device is deselected during erasure or program-
    ming, the device draws active current until the
    operation is completed.
    I
    CC3
    in the DC Characteristics table represents the
    standby current specification.
    Automatic Sleep Mode
    The automatic sleep mode minimizes Flash device
    energy consumption. The device automatically
    enables this mode when addresses remain stable for
    t
    ACC
    + 30 ns. The automatic sleep mode is
    independent of the CE#, WE#, and OE# control
    signals. Standard address access timings provide new
    data when addresses are changed. While in sleep
    mode, output data is latched and always available to
    the system. I
    CC4
    in the DC Characteristics table
    represents the automatic sleep mode current
    specification.
    RESET#: Hardware Reset Pin
    The RESET# pin provides a hardware method of re-
    setting the device to reading array data. When the RE-
    SET# pin is driven low for at least a period of t
    RP
    , the
    device
    immediately terminates
    any operation in
    progress, tristates all output pins, and ignores all
    read/write commands for the duration of the RESET#
    pulse. The device also resets the internal state ma-
    chine to reading array data. The operation that was in-
    terrupted should be reinitiated once the device is
    ready to accept another command sequence, to en-
    sure data integrity.
    Current is reduced for the duration of the RESET#
    pulse. When RESET# is held at V
    SS
    ±0.3 V, the device
    draws CMOS standby current (I
    CC4
    ). If RESET# is held
    at V
    IL
    but not within V
    SS
    ±0.3 V, the standby current will
    be greater.
    The RESET# pin may be tied to the system reset cir-
    cuitry. A system reset would thus also reset the Flash
    memory, enabling the system to read the boot-up firm-
    ware from the Flash memory.
    If RESET# is asserted during a program or erase op-
    eration, the RY/BY# pin remains a “0” (busy) until the
    internal reset operation is complete, which requires a
    time of t
    READY
    (during Embedded Algorithms). The sys-
    tem can thus monitor RY/BY# to determine whether
    the reset operation is complete. If RESET# is asserted
    when a program or erase operation is not executing
    (RY/BY# pin is “1”), the reset operation is completed
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