參數(shù)資料
型號(hào)： AM29LV033C-120FF
廠商： Advanced Micro Devices, Inc.
英文描述： 32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
中文描述： 32兆位（4個(gè)M × 8位）的CMOS 3.0伏特，只有統(tǒng)一部門(mén)閃存
文件頁(yè)數(shù)： 27/49頁(yè)
文件大?。?/td> 693K
代理商： AM29LV033C-120FF
22268B5 September 12, 2006
Am29LV033C
25
D A T A S H E E T
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
CC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data (includ-
ing during the Erase Suspend mode), or is in the
standby mode.
Table 10, on page 29
shows the outputs for RY/BY#.
Figures
“RESET# Timings” on page 35
,
Figure 15, on
page 37
and
Figure 17, on page 38
shows RY/BY# for
reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or
CE# to control the read cycles). When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 μs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 μs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 10, on page 29
shows the outputs for Toggle Bit
I on DQ6.
Figure 6, on page 28
shows the toggle bit al-
gorithm in flowchart form, and the section
“Reading
Toggle Bits DQ6/DQ2” on page 27
explains the algo-
rithm.
Figure 19, on page 39
in the “AC Characteris-
tics” section shows the toggle bit timing diagrams.
Figure 20, on page 39
shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on
“DQ2: Toggle Bit II”
.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but cannot dis-
tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode infor-
mation. Refer to
Table 10, on page 29
to compare out-
puts for DQ2 and DQ6.
Figure 6, on page 28
shows the toggle bit algorithm in
flowchart form, and the section
“Reading Toggle Bits
DQ6/DQ2”
explains the algorithm. See also the
“DQ6:
Toggle Bit I”
subsection.
Figure 19, on page 39
shows
the toggle bit timing diagram.
Figure 20, on page 39
shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 6, on page 28
for the following discus-
sion. Whenever the system initially begins reading tog-
gle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
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