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參數(shù)資料
| 型號： | AM29LV033MUU112RFI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control |
| 中文描述： | 32兆位（4個M × 8位）的MirrorBit 3.0伏特，只有統(tǒng)一閃存部門與VersatileI / O控制 |
| 文件頁數(shù)： | 11/56頁 |
| 文件大小： | 1138K |
| 代理商： | AM29LV033MUU112RFI |
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November 11, 2002
Am29LV033MU
11
A D V A N C E I N F O R M A T I O N
Refer to the DC Characteristics table for the active
current specification for reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 bytes. The appropriate page is selected
by the higher address bits A(max)–A3. Address bits
A2–A0 determine the specific byte within a page. This
is an asynchronous operation; the microprocessor
supplies the specific byte location.
The random or initial page access is equal to t
ACC
or
t
CE
and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to t
PACC
. When CE# is
deasserted and reasserted for a subsequent access,
the access time is t
ACC
or t
CE
. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
The device features an
Unlock Bypass
mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
Refer to the
DC Characteristics
table for the active
current specification for the write mode. The
AC Char-
acteristics
section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 32 bytes in one programming operation.
This results in faster effective programming time than
the standard programming algorithms. See “Write
Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the system asserts V
HH
on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
HH
from the ACC pin returns the device to normal op-
eration.
Note that the ACC pin must not be at V
HH
for
operations other than accelerated programming, or
device damage may result. In addition, the ACC pin
must not be left floating or unconnected; inconsistent
behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the
Autoselect Mode
and
Autose-
lect Command Sequence
sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
IO
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
IO
± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (t
CE
) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the
DC Characteristics
table for the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
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