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| 型號： | AM29LV065MU120RFI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| 中文描述： | 8M X 8 FLASH 3V PROM, 120 ns, PDSO48 |
| 封裝： | REVERSE, MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 34/62頁 |
| 文件大?。?/td> | 778K |
| 代理商： | AM29LV065MU120RFI |
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32
Am29LV065MU
September 12, 2006
D A T A S H E E T
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See “DQ3: Sector Erase
Timer” on page 37..). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or RY/BY# in the erasing sector. See “Write Op-
eration Status” on page 35. for information on these
status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a
hardware
reset
immediately
terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase opera-
tion. See the tables, “Erase and Program Operations”
on page 45 for parameters, and Figure 18 for timing di-
agrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 μs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a typi-
cal of 5 μs (maximum 20
μ
s) to suspend the erase op-
eration. However, when the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” on page 35. for informa-
tion on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard byte program operation. See
“Write Operation Status” on page 35. for more infor-
mation.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. See “Au-
toselect Mode” on page 17. and “Autoselect Com-
mand Sequence” on page 26 for details.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
Note: During an erase operation, this flash device per-
forms multiple internal operations which are invisible
to the system. When an erase operation is suspended,
any of the internal operations that were not fully com-
pleted must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative erase time than without suspends.
Note that the additional suspends do not affect device
reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In such
cases, erase performance will not be significantly im-
pacted.
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