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參數(shù)資料
| 型號： | AM29LV400B-90RWAC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 512K X 8 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 0.80 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AM29LV400B-90RWAC |
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Am29LV400
14
PREL I M I N AR Y
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Figure 2 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Note: See Table 5 for program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. Table 5 shows the address and data re-
quirements for the sector erase command sequence.
The device does
not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50
s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50
s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20514C-6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV400BB-120EC | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin TSOP |
| AM29LV400BB-120EI | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 48-Pin TSOP |
| AM29LV400BB-120SC | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 4Mbit 512K/256K x 8bit/16bit 120ns 44-Pin SOP |
| AM29LV400BB-120WAI | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 4M-Bit 512K x 8/256K x 16 120ns 48-Pin FBGA |
| AM29LV400BB-55RWAI | 制造商:Spansion 功能描述:SPZAM29LV400BB-55RWAI 4M FLASH EOL150606 |
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