參數(shù)資料
型號(hào): AM29LV640MT90REF
廠商: Advanced Micro Devices, Inc.
英文描述: 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Boot Sector Flash Memory
中文描述: 64兆位(4個(gè)M x 16位/八米× 8位)的MirrorBit⑩3.0伏,只引導(dǎo)扇區(qū)閃存
文件頁數(shù): 38/66頁
文件大?。?/td> 836K
代理商: AM29LV640MT90REF
36
Am29LV640MT/B
26190C8 February1,2007
D A T A S H E E T
Command Definitions
Table 12.
Command Definitions (x16 Mode, BYTE# = V
IH
)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on the falling edge of the WE#
or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
During unlock cycles, when lower address bits are 555 or 2AAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
No unlock or command cycles required when device is in read
mode.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except RD, PD and
WC. See
Autoselect Command Sequence on page 28
for more
information.
The device ID must be read in three cycles. The data is 2201h for
top boot and 2200h for bottom boot.
If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
4.
5.
6.
7.
8.
9.
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer. The
maximum number of cycles in the command sequence is 21,
including "Program Buffer to Flash" command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
15. The system can read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
17. Command is valid when device is ready to read array data or when
device is in autoselect mode.
Command Sequence
(Notes)
Read
(Note 5)
Reset
(Note 6)
Manufacturer ID
C
Bus Cycles (Notes
1
4
)
Third
Addr
Data
First
Second
Addr
Fourth
Fifth
Sixth
Addr
RA
XXX
555
Data
RD
F0
AA
Data
Addr
Data
Addr
Data
Addr
Data
1
1
4
A
(
2AA
55
555
90
X00
0001
Device ID
(Note 8)
6
555
AA
2AA
55
555
90
X01
227E
X0E
2210
X0F
2200/
2201
Secured Silicon Sector Factory
Protect
(Note 9)
Sector Group Protect Verify
(Note 10)
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
Write to Buffer
(Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset
(Note 12)
Unlock Bypass
Unlock Bypass Program
(Note 13)
Unlock Bypass Reset
(Note 14)
Chip Erase
Sector Erase
Program/Erase Suspend
(Note 15)
Program/Erase Resume
(Note 16)
CFI Query
(Note 17)
4
555
AA
2AA
55
555
90
X03
(Note 9)
4
555
AA
2AA
55
555
90
(SA)X02
00/01
3
4
4
6
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
555
555
XXX
XXX
555
555
XXX
XXX
55
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
SA
00
PD
WC
PA
PD
WBL
PD
2AA
2AA
PA
XXX
2AA
2AA
55
55
PD
00
55
55
555
555
F0
20
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
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