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參數(shù)資料
| 型號： | AM29LV640MT90REI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 4M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | MO-142B, TSOP-48 |
| 文件頁數(shù)： | 42/66頁 |
| 文件大?。?/td> | 836K |
| 代理商： | AM29LV640MT90REI |
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40
Am29LV640MT/B
26190C8 February1,2007
D A T A S H E E T
Figure 9.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system can use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to
Table 14
to compare out-
puts for DQ2 and DQ6.
Figure 9
shows the toggle bit algorithm in flowchart
form, and
DQ2: Toggle Bit II on page 40
explains the
algorithm. See also
RY/BY#: Ready/Busy# on
page 39
.
Figure 21
shows the toggle bit timing dia-
gram.
Figure 22
shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 9
for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high.
(See
DQ2: Toggle Bit II on page 40
.) If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit might have stopped tog-
gling just as DQ5 went high. If the toggle bit is no
longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to re-
turn to reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system can continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it can choose to perform
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note:
The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit can stop toggling as DQ5
changes to “1.” See
DQ6: Toggle Bit I
and
DQ2: Toggle Bit II
for more information.
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| AM29LV640MH120RFI | 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
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