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參數(shù)資料
| 型號(hào)： | AM29PDL127H |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位），3.0伏的CMOS只，頁(yè)面模式同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁(yè)數(shù)： | 42/68頁(yè) |
| 文件大?。?/td> | 750K |
| 代理商： | AM29PDL127H |
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June 30, 2003
Am29PDL127H
45
ADV ANCE
I N FO RMAT I O N
Table 15.
Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
Status
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY#
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Non-Erase
Suspended Sector
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
0
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