參數(shù)資料
型號(hào): AM29SL160C
廠商: Advanced Micro Devices, Inc.
英文描述: 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory
中文描述: 16兆位的CMOS 1.8伏只超低電壓快閃記憶體
文件頁(yè)數(shù): 13/52頁(yè)
文件大?。?/td> 1232K
代理商: AM29SL160C
November 1, 2004
Am29SL160C
13
RESET# pin is driven low for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
± 0.2 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
± 0.2 V, the standby current is
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to
“AC Characteristics” on page 37
for RESET#
parameters and to
“RESET# Timings” on page 38
for
the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
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AM29SL160CB-100 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory
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