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參數(shù)資料
| 型號： | AM29SL160CB-100WCIN |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| 中文描述： | 16兆位的CMOS 1.8伏只超低電壓快閃記憶體 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大?。?/td> | 1232K |
| 代理商： | AM29SL160CB-100WCIN |
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12
Am29SL160C
November 1, 2004
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See
“Reading Array Data” on page 23
for more infor-
mation. Refer to the AC table for timing specifications
and to
Figure 13, on page 37
for the timing diagram.
I
CC1
in the DC Characteristics table represents the
active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to
“Word/Byte Configuration” on page 11
for more information.
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” on
page 24
contains details on programming data to the
device using both standard and Unlock Bypass
command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 2, on page 14
and
Table 3, on page 15
indicate the address space that
each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector.
The
“Command Definitions” on page 23
contains
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to
“Autoselect Mode” on page 16
and
“Autoselect Command Sequence” on page 24
for
more information.
I
CC2
in the DC Characteristics table represents the
active current specification for the write mode. The
“AC
Characteristics” on page 37
contains timing specifica-
tion tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operation
through the ACC function, which is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster in-system programming of
the device during the system production process.
If the system asserts V
HH
on the pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the pin to reduce
the time required for program operations. The system
would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
HH
from the WP#/ACC pin returns the device to normal
operation.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to
“Write Operation
Status” on page 29
for more information, and to
“AC
Characteristics” on page 37
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
±
0.2 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
±
0.2 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (t
CE
) for read access when the device
is in either of these standby modes, before it is ready to
read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to
“RESET#: Hard-
ware Reset Pin” on page 12
.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
ACC
+ 50 ns. The automatic sleep mode is independent
of the CE#, WE#, and OE# control signals. Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system. I
CC4
in the DC Characteristics table represents the auto-
matic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
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