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參數(shù)資料
| 型號： | Am29SL800CB150FIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Hex Inverters 14-PDIP -55 to 125 |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），1.8伏的CMOS只超低電壓快閃記憶體 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 549K |
| 代理商： | AM29SL800CB150FIB |
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Am29SL800C
9
P R E L I M I N A R Y
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more infor-
mation.
The device features an
Unlock Bypass
mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to pro-
gram a word or byte, instead of four. The “Word/Byte Pro-
gram Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors,
or the entire device. Tables 2 and 3 indicate the address
space that each sector occupies. A “sector address” con-
sists of the address bits required to uniquely select a sector.
The “Command Definitions” section has details on erasing
a sector or the entire chip, or suspending/resuming the
erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The sys-
tem can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the active
current specification for the write mode. The “AC Charac-
teristics” section contains timing specification tables and
timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7–DQ0. Standard read cycle timings and I
CC
read
specifications apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics” for timing di-
agrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
OE# input.
The device enters the CMOS standby mode when the CE#
and RESET# pins are both held at V
CC
±
0.3 V. (Note that
this is a more restricted voltage range than V
IH
.) If CE# and
RESET# are held at V
IH
, but not within V
CC
±
0.3 V, the de-
vice will be in the standby mode, but the standby current will
be greater. The device requires standard access time (t
CE
)
for read access when the device is in either of these
standby modes, before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, RESET#:
Hardware Reset Pin.
If the device is deselected during erasure or programming,
the device draws active current until the operation is com-
pleted.
I
CC3
in the DC Characteristics table represents the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+ 50 ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. I
CC4
in the DC Characteristics table represents
the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the RESET# pin is
driven low for at least a period of t
RP
, the device
immedi-
ately terminates
any operation in progress, tristates all
output pins, and ignores all read/write commands for the
duration of the RESET# pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V
SS
±0.3 V, the device draws
CMOS standby current (I
CC4
). If RESET# is held at V
IL
but
not within V
SS
±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET# is asserted during a program or erase opera-
tion, the RY/BY# pin remains a “0” (busy) until the internal
reset operation is complete, which requires a time of
t
READY
(during Embedded Algorithms). The system can
thus monitor RY/BY# to determine whether the reset oper-
ation is complete. If RESET# is asserted when a program
or erase operation is not executing (RY/BY# pin is “1”), the
reset operation is completed within a time of t
READY
(not
during Embedded Algorithms). The system can read data
t
RH
after the RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# param-
eters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is dis-
abled. The output pins are placed in the high impedance
state.
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