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參數(shù)資料
| 型號： | AM29SL800DT-100WCI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），1.8伏的CMOS只超低電壓快閃記憶體 |
| 文件頁數(shù)： | 10/46頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | AM29SL800DT-100WCI |
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A D V A N C E I N F O R M A T I O N
March 17, 2003
Am29SL800D
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29SL800D Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 10
±
1.0 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
The sector protect and sector unprotect functions may also be implemented via programming equipment.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
IH
. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
Operation
CE#
L
L
V
CC
±
0.2 V
L
X
OE# WE# RESET#
L
H
H
L
Addresses
(Note 1)
A
IN
A
IN
DQ0–
DQ7
D
OUT
D
IN
DQ8–DQ15
BYTE#
= V
IH
D
OUT
D
IN
BYTE#
= V
IL
Read
Write
H
H
DQ8–DQ14 = High-Z,
DQ15 = A-1
Standby
X
X
V
CC
±
0.2 V
H
L
X
High-Z
High-Z
High-Z
Output Disable
Reset
H
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Protect (Note )
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
D
IN
X
X
Sector Unprotect (Note )
L
H
L
V
ID
D
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
D
IN
D
IN
High-Z
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