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product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
Publication#
25870
Issue Date:
February 13, 2002
Rev:
A
Amendment/
0
Am41DL3208G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Power supply voltage of 2.7 to 3.3 volt
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High performance
— Access time as fast as 70 ns
Package
— 73-Ball FBGA
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Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
Flexible Bank
TM
architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
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Secured Silicon (SecSi) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
—
Customer lockable:
Sector is one-time programmable. Once
locked, data cannot be changed
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Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
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Top or bottom boot block
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Manufactured on 0.17 μm process technology
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Compatible with JEDEC standards
—
Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
—
Access time as fast as 70 ns
—
Program time: 4 μs/word typical utilizing Accelerate function
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Ultra low power consumption (typical values)
—
2 mA active read current at 1 MHz
—
10 mA active read current at 5 MHz
—
200 nA in standby or automatic sleep mode
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Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125
°
C
—
Reliable operation for the life of the system
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SOFTWARE FEATURES
Data Management Software (DMS)
—
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
—
Eases sector erase limitations
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Supports Common Flash Memory Interface (CFI)
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Unlock Bypass Program command
—
Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
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Ready/Busy# output (RY/BY#)
—
Hardware method for detecting program or erase cycle
completion
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Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
reading array data
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WP#/ACC input pin
—
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
—
Acceleration (ACC) function accelerates program timing
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Sector protection
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
Power dissipation
—
Operating: 30 mA maximum
—
Standby: 15 μA maximum
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CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)