參數(shù)資料
型號(hào)： AM41DL6408G40IT
廠商： Advanced Micro Devices, Inc.
英文描述： 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
中文描述： 64兆位（8米× 8位/ 4米x 16位），3.0伏的CMOS只，同時(shí)作業(yè)閃存和8兆位（1 M中的x 8-Bit/512畝x 16位），靜態(tài)存儲(chǔ)器
文件頁數(shù)： 4/63頁
文件大?。?/td> 573K
代理商： AM41DL6408G40IT
August 19, 2002
Am41DL6408G
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
flash memory Block Diagram . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .7
Special Handling Instructions for FBGA Package ....................7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAMWord Mode, CIOs = V
CC
..................................................... 10
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAMByte Mode, CIOs = V
SS
......................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAMWord Mode, CIOs = V
CC
.....................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
SS
..................................................................13
Word/Byte Configuration ........................................................13
Requirements for Reading Array Data ...................................13
Writing Commands/Command Sequences ............................14
Accelerated ProgramOperation ..........................................14
Autoselect Functions ...........................................................14
Simultaneous Read/Write Operations with Zero Latency .......14
Standby Mode ........................................................................14
Automatic Sleep Mode ...........................................................15
RESET# Hardware Reset Pin ...............................................15
Output Disable Mode ..............................................................15
Table 5. Am29DL640G Sector Architecture ....................................15
Table 6. Bank Address ....................................................................18
Table 7. SecSi
Sector Addresses ...............................................18
Sector/Sector Block Protection and Unprotection ..................19
Table 8. Am29DL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................19
Write Protect (WP#) ................................................................20
Table 9. WP#/ACC Modes ..............................................................20
Temporary Sector Unprotect ..................................................20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-SystemSector Protect/Unprotect Algorithms.............. 21
SecSi (Secured Silicon) Sector
FlashMemoryRegion ............................................................22
Hardware Data Protection ......................................................22
Low V
CC
Write Inhibit ...........................................................22
Write Pulse “Glitch” Protection ............................................23
Logical Inhibit ......................................................................23
Power-Up Write Inhibit .........................................................23
Common Flash Memory Interface (CFI) . . . . . . .23
Table 10. CFI Query Identification String........................................ 23
SystemInterface String................................................................... 24
Table 12. Device Geometry Definition............................................ 24
Table 13. Primary Vendor-Specific Extended Query...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................26
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..
26
Byte/Word ProgramCommand Sequence .............................27
Unlock Bypass Command Sequence ..................................27
Figure 3. ProgramOperation......................................................... 28
Chip Erase Command Sequence ...........................................28
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................29
Figure 4. Erase Operation.............................................................. 29
Table 14. Am29DL640G Command Definitions.............................. 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data#Polling .................................................................31
Figure 5. Data#Polling Algorithm.................................................. 31
RY/BY# Ready/Busy#............................................................32
DQ6: Toggle Bit I ....................................................................32
Figure 6. Toggle Bit Algorithm....................................................... 32
DQ2: Toggle Bit II ...................................................................33
Reading Toggle Bits DQ6/DQ2 ...............................................33
DQ5: Exceeded Timng Limts ................................................33
DQ3: Sector Erase Timer .......................................................33
Table 15. Write Operation Status ...................................................34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. MaximumNegative OvershootWaveform...................... 35
Figure 8. MaximumPositive OvershootWaveform........................ 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
CMOS Compatible ..................................................................36
SRAM DC and Operating Characteristics . . . . . 38
Figure 9. I
CC1
Current vs. Time (Showing Active and
AutomaticSleepCurrents)............................................................. 39
Figure 10. Typical I
vs. Frequency............................................ 39
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Figure 12. Input Waveforms and Measurement Levels................. 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAMCE#s Timng ................................................................41
Figure 13. Timng Diagramfor Alternating Between SRAMto Flash..
41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Read-Only Operations .................................................42
Figure 14. Read Operation Timngs............................................... 42
Hardware Reset (RESET#) ....................................................43
Figure 15. Reset Timngs............................................................... 43
Word/Byte Configuration (CIOf) ..............................................44
Figure 16. CIOf Timngs for Read Operations................................ 44
Figure 17. CIOf Timngs for Write Operations................................ 44
Erase and ProgramOperations ..............................................45
Figure 18. ProgramOperation Timngs.......................................... 46
Figure 19. Accelerated ProgramTimng Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timngs.......................... 47
Figure 21. Back-to-back Read/Write Cycle Timngs...................... 48
Figure 22. Data#Polling Timngs (During Embedded Algorithms). 48
Figure 23. Toggle Bit Timngs (During Embedded Algorithms)...... 49
Figure 24. DQ2 vs. DQ6................................................................. 49
Temporary Sector Unprotect ..................................................50
Figure 25. Temporary Sector Unprotect Timng Diagram.............. 50
Figure 26. Sector/Sector Block Protect and
Unprotect Timng Diagram............................................................. 51
Alternate CE#f Controlled Erase and ProgramOperations ....52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program
OperationTimngs.......................................................................... 53
SRAMRead Cycle ..................................................................54
Figure 28. SRAMRead Cycle—Address Controlled...................... 54
Figure 29. SRAMRead Cycle........................................................ 55
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM41DL6408G45IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G45IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G55IS 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G55IT 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
AM41DL6408G70IS 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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