參數(shù)資料
型號(hào): AM41PDS3224DT11IT
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 59/59頁
文件大?。?/td> 1072K
代理商: AM41PDS3224DT11IT
8
Am41PDS3224D
May 13, 2002
P R E L IMINARY
PIN DESCRIPTION
A17–A0
= 18 Address Inputs (Common)
A20–A18
= 3 Address Inputs (Flash)
SA
= Highest Order Address Pin (SRAM)
Byte mode
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f
= Chip Enable (Flash)
CE1#s
= Chip Enable 1 (SRAM)
CE2s
= Chip Enable 2 (SRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output (Flash)
UB#s
= Upper Byte Control (SRAM)
LB#s
= Lower Byte Control (SRAM)
CIOs
= I/O Configuration (SRAM)
CIOs = V
IH = Word mode (x16),
CIOs = V
IL = Byte mode (x8)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 1.8 volt-only single power
supply (see Product Selector Guide
for speed options and voltage sup-
ply tolerances)
V
CCs
= SRAM Power Supply
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
18
16 or 8
DQ15–DQ0
A17–A0
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A20–A18
LB#s
CIOs
CE1#s
CE2s
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