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參數(shù)資料
| 型號： | Am53CF96JCW |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced SCSI-2 Controller (ESC) |
| 中文描述： | 增強型SCSI - 2控制器（調(diào)速器） |
| 文件頁數(shù)： | 23/76頁 |
| 文件大小： | 735K |
| 代理商： | AM53CF96JCW |
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P R E L I M I N A R Y
AMD
23
Am53CF94/Am53CF96
SCSI Timeout Register (05H) Write
SCSI Timeout Register
STIMREG
7
Address: 05
H
Type: Write
0
6
5
4
3
2
1
STIM7
STIM6
STIM5
STIM4
STIM3
STIM2
STIM1
STIM0
x
x
x
x
x
x
x
x
17348B-23
This register determines how long the Initiator (Target)
will wait for a response to a Selection (Reselection)
before timing out. It should be set to yield 250 ms to
comply with ANSI standards for SCSI, but the maximum
time out period may be calculated using the following
formulas.
Note:
A hardware reset will clear this register.
STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0
The value loaded in STIM 7:0 can be calculated as
shown below:
STIM 7:0 =
[(SCSI Time Out) (Clock Frequency) / (8192 (Clock
Factor))]
Example:
SCSI Time Out (in seconds): 250 ms. (Recommended
by the ANSI Standard) = 250 x 10
–3
s.
Clock Frequency: 20 MHz. (assume) = 20 x 10
6
Hz.
Clock Factor: CLKF 2:0 from Clock Conversion Register
(09H) = 5
STIM 7:0 = (250 x 10
–3
)
X (20 x 10
6
) / (8192 (5)) = 122
decimal
Internal State Register (06H) Read
Internal State Register
ISREG
Address: 06
H
Type: Read
7
6
5
4
3
2
1
0
RES
RES
RES
RES
SOF
IS2
IS1
IS0
x
x
x
x
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Synchronous Offset Flag
Internal State 2:0
17348B-24
The Internal State Register (ISREG) tracks the progress
of a sequence-type command. It is updated after each
successful completion of an intermediate operation. If
an error occurs, the host can read this register to
determine the point where the command failed and take
the necessary procedure for recovery. Reading the
Interrupt Status Register (INSTREG) while an interrupt
is pending will clear this register. A hard or soft reset will
also zero this register .
ISREG – Bits 7:4 – RES – Reserved
ISREG – Bit 3 –
SOF
– Synchronous Offset Flag
The SOF is reset when the Synchronous Offset Register
(SOFREG) has reached its maximum value.
Note:
The SOF bit is active Low.
ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0
The IS 2:0 bits along with the Interrupt Status Register
(INSTREG) indicates the status of the successfully
completed intermediate operation. Refer to the Status
Decode section for more details.
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| AM53CF96KC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: 制造商:AMD 功能描述: |
| AM53CF96KCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced SCSI-2 Controller (ESC) |
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