參數(shù)資料
型號(hào): AM79574
廠商: Advanced Micro Devices, Inc.
英文描述: Subscriber Line Interface Circuit
中文描述: 用戶線接口電路
文件頁(yè)數(shù): 11/17頁(yè)
文件大小: 162K
代理商: AM79574
SLIC Products
11
11. Assumes the following Z
T
network:
12. Tested with 0
source impedance. 2 M
is specified for system design purposes only.
13. Group delay can be considerably reduced by using a Z
T
network such as that shown in Note 11 above. The network reduces
the group delay to less than 2
μ
s. The effect of group delay on linecard performance may be compensated for by using
QSLAC
or DSLAC
devices.
Note:
*
A logic Low on E0 disables the DET output into the Open Collector state.
Table 1.
SLIC Decoding
DET Output
State
C3 C2 C1
Two-Wire Status
E0 = 1*
E1 = 0
E0 = 1*
E1 = 1
0
0 0 0
Open Circuit
Ring trip
Ring trip
1
0 0 1
Ringing
Ring trip
Ring trip
2
0 1 0
Active
Loop detector
Ground key
3
0 1 1
On-hook TX (OHT)
Loop detector
Ground key
4
1 0 0
Tip Open
Loop detector
5
1 0 1
Reserved
Loop detector
6
1 1 0
Active Polarity Reversal
Loop detector
Ground key
7
1 1 1
OHT Polarity Reversal
Loop detector
Ground key
Table 2.
User-Programmable Components
Z
T
is connected between the VTX and RSN pins. The fuse
resistors are R
F
, and Z
2WIN
is the desired 2-wire AC input
impedance. When computing Z
T
, the internal current
amplifier pole and any external stray capacitance between
VTX and RSN must be taken into account.
Z
RX
is connected from VRX to the RSN pin, Z
T
is defined
above, and G
42L
is the desired receive gain.
R
DC1
, R
DC2
, and C
DC
form the network connected to the
RDC pin. R
DC1
and R
DC2
are approximately equal.
R
D
and C
D
form the network connected from RD to
5 V and
I
T
is the threshold current between on hook and off hook.
VTX
RSN
300 k
300 k
30 pF
Z
T
1000 Z
2WIN
2R
F
)
=
Z
RX
Z
G
42L
-----------
1000
1000 Z
L
Z
T
2R
F
+
)
+
----------------------------------------------------
=
R
DC1
R
DC2
50 R
FEED
2R
F
)
=
+
C
DC
1.5 ms
R
R
DC1
R
DC2
-------------------------------
=
R
D
I
T
--------
C
D
R
D
-----------------
=
,
=
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