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參數(shù)資料
| 型號： | AM79C875KI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大小： | 2480K |
| 代理商： | AM79C875KI |
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Am79C875
Within the NetPHY 4LP device, this block is repli-
cated for each port. The RMII signals should be taken
in context with the port being referred.
The 100BASE-X block consists of the following
sub-blocks:
— Transmit Process
— Receive Process
— Internal Loopback Paths
— 4B/5B Encoder and Decoder
— Scrambler/Descrambler
— Link Monitor
— Far End Fault Generation and Detection &
Code-Group Generator
— MLT-3 encoder/decoder with Adaptive Equaliza-
tion
— Serializer/Deserializer and Clock Recovery
— Baseline Restoration
Transmit Process
The transmit process generates code-groups based on
the transmit control and data signals on the RMII. This
process is also responsible for frame encapsulation
into a Physical Layer Stream, generating the collision
signal based on whether a carrier is received simulta-
neously with transmission and generating the Carrier
Sense CRS signal at the RMII. The transmit process is
implemented in compliance with the transmit state dia-
gram as defined in Clause 24 of the IEEE 802.3u spec-
ification.
Receive Process
The receive process passes to the RMII a sequence of
data derived from the incoming code-groups. Each
code-group is comprised of five code-bits. This process
detects channel activity and then aligns the incoming
code bits in code-group boundaries for subsequent
data decoding. The receive process is responsible for
code-group alignment and also generates the Carrier
Sense (CRS) signal at the RMII. The receive process
is implemented in compliance with the receive state di-
agram as defined in Clause 24 of the IEEE 802.3u
specification. The False Carrier Indication as specified
in the standard is also generated by this block, and
communicated to the Reconciliation layer through RXD
and RX_ER.
Encoder/Decoder
The 100 Mbps process in the NetPHY 4LP device
uses the 4B/5B encoding scheme as defined in IEEE
802.3, Section 24. This scheme converts between raw
data on the RMII and encoded data on the media pins.
The encoder converts raw data to the 4B/5B code. It
also inserts the stream boundary delimiters (/J/K/ and /
T/R/) at the beginning and end of the data stream as
appropriate. The decoder converts between encoded
data on the media pins and raw data on the RMII. It also
detects the stream boundary delimiters to help deter-
mine the start and end of packets.
The code-group mapping is defined in Table 1.
Scrambler/Descrambler
The 4B/5B encoded data has repetitive patterns which
result in peaks in the RF spectrum large enough to
keep the system from meeting the standards set by
regulatory agencies such as the FCC. The peaks in the
radiated signal are reduced significantly by scrambling
the transmitted signal. Scramblers add the output of a
random generator to the data signal. The resulting
signal has fewer repetitive data patterns.
After reset, the scrambler seed in each port will be set
to the PHY address value to help improve the EMI
performance of the device.
The scrambled data stream is descrambled, at the re-
ceiver, by adding it to the output of another random
generator. The receiver’s random generator has the
same function as the transmitter’s random generator.
The scrambler/descrambler configuration is set by the
SCRAM_EN pin and the EN_SCRM bit (Register 24,
bit 2). The SCRAM_EN pin is latched at the rising edge
of the RST signal. The scrambler/descrambler can be
enabled if SCRAM_EN latches above 2.0 V. Otherwise,
they are all disabled. The EN_SCRM bit sets the
scrambler/descrambler configuration for the corre-
sponding port. The bit defaults to 1 at reset.
The scrambler/descrambler can only be enabled when
the port is in the 100-Mbps MLT-3 mode. The scrambler
is disabled on any port that has a link at 10 Mbps or any
port that is forced to 10 Mbps.
Link Monitor
Signal levels are qualified using squelch detect circuits.
A signal detect (SD) circuit following the equalizer is
asserted high whenever the peak detector detects a
post-equalized signal with peak-to-ground voltage level
larger than 400 mV, which is about 40% of the normal
signal voltage level, and the energy level is sustained
longer than 2 ~ 3 ms. It is deasserted approximately
1 ms to 2 ms after the energy level detected in the re-
ceiving lines is consistently less than 300 mV peak.
The signal is forced to low during a local loopback op-
eration (Register 0, bit 14 Loopback is asserted) and
forced to high when a remote Loopback is taking place
(Register 24, bit 3 EN_RPBK is set).
In 100BASE-TX mode, when no signal or invalid sig-
nals are detected on the receive pair, the link monitor
will enter in the “l(fā)ink fail” state where only link pulses
will be transmitted. Otherwise, when a valid signal is
detected for a minimum period of time, the link monitor
will then enter link pass state which transmit and
receive functions will be entered.
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