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參數(shù)資料
| 型號： | AM79C901AJIT |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| 中文描述： | HomePHY單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)物理層 |
| 文件頁數(shù)： | 18/90頁 |
| 文件大小： | 714K |
| 代理商： | AM79C901AJIT |
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18
Am79C901A
P R E L I M I N A R Y
PIN DESCRIPTIONS
Configuration Pins
MII/GPSI
MII/GPSI
MII/GPSI selects between the MII and the GPSI inter-
face. This pin must be connected to either V
DD
or V
SS
.
Changing the state of this pin is prohibited.
GM_MODE
GM_MODE
This input pin selects between the MDC/MDIO com-
mand and control interface and
the SPI interface nor-
mally available in the GPSI mode. This pin must be
connected to either V
DD
or V
SS
. Changing the state of
this pin is prohibited.
Input
Input
Note:
GM_MODE = 1 overrides the value on the
MII/GPSI configuration pin.
PHY_AD
PHY Address
Sets bit 2 of the PHY Address field. The PHYs have de-
fault MII address of 0x00 (0000b) for the 1 Mbps
HomePNA PHY and 0x01 (0001b) for the 10BASE-T
PHY. If this bit is set, the address for the HomePNA
PHY is 0x02 (00010b) and 0x03 (00011b) for the
10BASE-T PHY.
ISOLATE
Isolate
In an environment that utilizes the MII or the SPI com-
mand and control interface (managed mode), this pin
must be held HIGH. In an environment that does not
use the MII or the SPI command and control interface
(external control mode), this pin enables the data inter-
face when set to a LOW, and forces the interface into a
high impedance state when held HIGH. This pin func-
tions in conjunction with the PHY_SEL pin and HPR0,
bit 10, and TBR0, bit 10.
PHY_SEL
PHY Select
In an environment that utilizes the MII or the SPI com-
mand and control interface (managed mode), this pin
must be held LOW. In an environment that does not use
Input
Input
Input
the MII or the SPI command and control interface (ex-
ternal control mode), this pin selects which PHY data
and status signals will be driven onto the interface.
When set to a LOW, the HomePNA PHY data and sta-
tus signals will be driven onto the interface. When set
to a HIGH, the 10BASE-T PHY data and status signals
will be driven onto the interface. This pin functions in
conjunction with the ISOLATE pin.
LOW = 1 Mbps HomePNA PHY
HIGH = 10BASE-T PHY
Board Interface
LED_COL
LED_COL
This output is designed to directly drive an LED. COL
low indicates that a collision has been detected on
the currently active PHY. An internal pulse stretching
circuit will ensure that the minimum output pulse is
approximately 100 ms.
LED_ACTIVITY
LED_ACTIVITY
This output is designed to directly drive an LED.
ACTIVITY low indicates that there is receive or trans-
mit activity on the network of the currently active PHY.
An internal pulse stretching circuit will ensure that the
minimum output pulse is approximately 100 ms.
LED_LINK
LED_LINK
This output is designed to directly drive an LED. LINK
low indicates that a valid link has been detected on the
currently active PHY.
Output
Output
Output
GM_MODE
MII/GPSI
Data
Interface
Command and
Control Interface
0
1
MII
MDC/MDIO
0
0
GPSI
SPI
1
X
GPSI
MDC/MDIO
HPR0
Bit 10
TBR0
Bit 10
PHY_SEL
ISOLATE
Interface
Source
Managed Mode
1
1
0
1
Hi Z
0
1
0
1
1 Mbps
HomePNA
1
0
0
1
10BASE-T
0
0
0
1
Non Valid
External Control Mode
1
1
1
0
10BASE-T
1
1
0
0
1 Mbps
HomePNA
1
1
Don
’
t
Care
1
Hi Z
相關(guān)PDF資料 |
PDF描述 |
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| AM79C901AVC | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVCT | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVI | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVIT | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C901AVC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVC/w | 制造商:Advanced Micro Devices 功能描述:79C901AVC/W |
| AM79C901AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C901AVC\W | 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 1Mbps/10Mbps 80-Pin TQFP |
| AM79C901AVCT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
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