參數(shù)資料
型號(hào): AM79C901AVIT
廠商: Advanced Micro Devices, Inc.
英文描述: HomePHY Single-Chip 1/10 Mbps Home Networking PHY
中文描述: HomePHY單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)物理層
文件頁(yè)數(shù): 81/90頁(yè)
文件大?。?/td> 714K
代理商: AM79C901AVIT
Am79C901A
81
P R E L I M I N A R Y
AC CHARACTERISTICS (CONTINUED)
1 Mbps HomePNA Clock Timing (MII)
Note:
During AID interval, RX_CLK and TX_CLK stop for up to 140
μ
s.
Figure 15.
1 Mbps HomePNA Clock Timing (MII)
No.
Symbol
Parameter Description
Clock Period
Unit
Idle (excluding IPG time)
74
t
PER
TX_CLK, RX_CLK period
2333.34
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
1165
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
1168
ns
Preamble (first 64 bits of TX MAC frame)
74
t
PER
TX_CLK, RX_CLK period
933.33
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467
ns
Data (throughout the data phase)
74
t
PER
TX_CLK, RX_CLK period
933 ns - 40
μ
s
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466 ns - 40
μ
s
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467 ns - 40
μ
s
IPG (96 bit times following CRS falling edge)
74
t
PER
TX_CLK, RX_CLK period
933.33
ns
75
t
PWH
TX_CLK, RX_CLK pulse width HIGH
466
ns
76
t
PWL
TX_CLK, RX_CLK pulse width LOW
467
ns
TX_CLK,
RX_CLK
74
76
75
22304B-39
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