參數(shù)資料
型號(hào): AM79C90PCTR
廠商: Advanced Micro Devices, Inc.
英文描述: CMOS Local Area Network Controller for Ethernet (C-LANCE)
中文描述: 的CMOS局域網(wǎng)控制器(丙應(yīng)聘以太網(wǎng))
文件頁數(shù): 38/62頁
文件大?。?/td> 437K
代理商: AM79C90PCTR
AMD
P R E L I M I N A R Y
38
Am79C90
SWITCHING CHARACTERISTICS
Parameter
Symbol
Test
No.
Parameter Description
Conditions
Min
Typ
Max
Unit
1
t
TCT
TCLK Period
99
101
ns
2
t
TCL
TCLK LOW Time
45
55
ns
3
t
TCH
TCLK HIGH Time
45
55
ns
4
t
TCR
Rise Time of TCLK
(Note 3)
8
ns
5
t
TCF
Fall Time of TCLK
(Note 3)
8
ns
6
t
TEP
TENA Propagation Delay After the
Rising Edge of TCLK
60
ns
7
t
TEH
TENA Hold Time After the Rising
Edge of TCLK
5
ns
8
t
TDP
TX Data Propagation Delay After the
Rising Edge of TCLK
60
ns
9
t
TDH
TX Data Hold Time After the Rising
Edge of TCLK
5
ns
10
t
RCT
RCLK Period
(Note 3)
85
118
ns
11
t
RCH
RCLK HIGH Time
(Note 2)
38
ns
12
t
RCL
RCLK LOW Time
(Note 2)
38
ns
13
t
RCR
Rise Time of RCLK
(Note 3)
8
ns
14
t
RCF
Fall Time of RCLK
(Note 3)
8
ns
15
t
RDR
RX Data Rise Time
(Note 3)
8
ns
16
t
RDF
RX Data Fall Time
(Note 3)
8
ns
17
t
RDH
RX Data Hold Time (RCLK to RX
Data Change)
(Note 2)
5
ns
18
t
RDS
RX Data Setup Time (RX Data Stable
to the Rising Edge of RCLK)
(Note 2)
35
ns
19
t
DPL
RENA LOW Time
1t
TCT
+ 20
ns
20
t
CPH
CLSN HIGH Time
80
ns
21
t
DOFF
Bus Master Driver Disable After Rising
Edge of
HOLD
50
ns
22
t
DON
Bus Master Driver Enable After Falling
Edge of
HLDA
50
2t
TCT
+ 50
ns
23
t
HHA
Delay to Falling Edge of
HLDA
from
Falling Edge of
HOLD
(Bus Master)
0
ns
24
t
RW
RESET
Pulse Width LOW
(Note 7)
2t
TCT
ns
25
t
CYCLE
Read/Write, Address/Data Cycle Time
(Note 1)
6t
TCT
ns
26
t
XAS
Address Setup Time to the Falling
Edge of ALE
75
ns
27
t
XAH
Address Hold Time After the Rising
Edge of
DAS
35
ns
28
t
AS
Address Setup Time to the Falling
Edge of ALE
75
ns
29
t
AH
Address Hold Time After the Falling
Edge of ALE
35
ns
30
t
RDAS
Data Setup Time to the Rising Edge
of
DAS
(Bus Master Read)
40
ns
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