參數(shù)資料
型號： AM79C961A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
中文描述： PCnet⑩- 2跳線的ISA，全雙工單芯片以太網(wǎng)控制器為ISA
文件頁數(shù)： 73/85頁
文件大小： 1088K
代理商： AM79C961A
Am79C961A
73
P R E L I M I N A R Y
there are link beat pulses or valid frames present. This
LED0 pin can be used to drive a LED and/or external
hardware that directly controls the SLEEP pin of the
PCnet-ISA II controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link.
Access Operations (Software)
We begin by describing how byte and word data are
addressed on the ISA bus, including conversion cycles
where 16-bit accesses are turned into 8-bit accesses
because the resource accessed did not support 16-bit
operations. Then we describe how registers and other
resources are accessed. This section is for the device
programmer, while the next section (bus cycles) is for
the hardware designer.
I/O Resources
The PCnet-ISA II controller has both I/O and memory
resources. In the I/O space the resources are orga-
nized as indicated in the following table:
The PCnet-ISA II controller does not respond to any
addresses outside of the offset range 0-17h. I/O offsets
18h and up are not used by the PCnet-ISA II controller.
I/O Register Access
The register address port (RAP) is shared by the regis-
ter data port (RDP) and the ISACSR data port (IDP) to
save registers. To access the Ethernet controller’s RDP
or IDP, the RAP should be written first, followed by the
read or write access to the RDP or IDP. I/O register
accesses should be coded as 16-bit accesses, even if
the PCnet-ISA II controller is hardware configured for
8-bit I/O bus cycles. It is acceptable (and transparent)
for the motherboard to turn a 16-bit software access
into two separate 8-bit hardware bus cycles. The moth-
erboard accesses the low byte before the high byte and
the PCnet-ISA II controller has circuitry to specifically
support this type of access.
The reset register causes a reset when read. Any value
will be accepted and the cycle may be 8 or 16 bits wide.
Writes are ignored.
All PCnet-ISA II controller register accesses should be
coded as 16-bit operations.
“Note that the RAP is cleared on Reset.”
IEEE Address Access
The address PROM may be an external memory
device that contains the node’s unique physical Ether-
net address and any other data stored by the board
manufacturer. The software accesses must be 16-bit.
This information may be stored in the EEPROM.
Boot PROM Access
The boot PROM is an external memory resource
located by the address selected by the EEPROM or the
BPAM input in
slave
mode. It may be software
accessed as an 8-bit or 16-bit resource but the latter is
recommended for best performance.
Static RAM Access
The static RAM is only present in the Bus Slave mode.
In the Bus Slave mode, two SRAM access schemes
are available. When the Shared Memory architecture
mode is selected, the SRAM is accessed using ISA
memory cycles to the address range selected by the
SMAM input. It may be accessed as an 8 or 16-bit
resource but the latter is recommended for best perfor-
mance. When the Programmed I/O architecture mode
is selected, the SRAM is accessed through ISACSR0
and ISACSR1 using the RAP and IDP.
Bus Cycles (Hardware)
The PCnet-ISA II controller supports both 8-bit and
16-bit hardware bus cycles. The following sections out-
line where any limitations apply based upon the archi-
tecture mode and/or the resource that is being
accessed (PCnet-ISA II controller registers, address
PROM, boot PROM, or shared memory SRAM). For
completeness, the following sections are arranged by
architecture (Bus Master Mode or Bus Slave Mode).
SRAM resources apply only to Bus Slave Mode.
All resources (registers, PROMs, SRAM) are pre-
sented to the ISA bus by the PCnet-ISA II controller.
With few exceptions, these resources can be config-
ured for either 8-bit or 16-bit bus cycles. The I/O
resources (registers, address PROM) are width config-
ured using the EEPROM. The memory resources (boot
PROM, SRAM) are width configured by external hard-
ware.
For 16-bit memory accesses, hardware external to the
PCnet-ISA II controller asserts MEMCS16 when either
of the two memory resources is selected. The ISA bus
requires that all memory resources within a block of
128 Kbytes be the same width, either 8- or 16-bits. The
reason for this is that the MEMCS16 signal is generally
a decode of the LA
17-23
address lines. 16-bit memory
capability is desirable since two 8-bit accesses take the
same amount of time as four 16-bit accesses.
All accesses to 8-bit resources (which do not return
MEMCS16 or IOCS16) use SD0-7. If an odd byte is
accessed, the Current Master swap buffer turns on.
Offset
#Bytes
Register
0h
16
IEEE Address
10h
2
RDP
12h
2
RAP(shared by RDP and IDP)
14h
2
Reset
16h
2
IDP
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