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參數(shù)資料
| 型號： | AM79C982-8JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | basic Integrated Multiport Repeater (bIMR) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 254K |
| 代理商： | AM79C982-8JC |
Am79C982
1–9
P R E L I M I N A R Y
PIN DESCRIPTION
ACK
Acknowledge
Input, Active LOW
When this input is asserted, it signals to the requesting
b
IMR device that it may control the DAT and JAM pins.
If the
b
IMR chip is not requesting control of the DAT line
(REQ pin HIGH), then the assertion of the ACK signal
indicates the presence of valid collision status on the
JAM or valid data on the DAT line.
AV
DD
Analog Power
Power Pin
These pins supply +5 V to the RXD+/– receivers, the
DI+/– and CI+/– receivers, the DO+/– drivers, the inter-
nal PLL, and the internal voltage reference of the
device. These power pins should be decoupled and
kept separate from other power and ground planes.
AV
SS
Analog Ground
Ground Pin
These pins are the 0 V reference for AV
COL
Expansion Collision
Input, Active LOW
When this input is asserted by an external arbiter, it sig-
nifies that more than one
b
IMR device is active and that
each
b
IMR device should generate the Collision Jam
sequence independently.
CI+, CI–
Control In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
CRS
Carrier Sense
Output
The states of the internal carrier sense signals for the
AUI port and the eight twisted-pair ports are serially
output on this pin continuously. The output serial bit
stream is synchronized to the X
b
IMR
DD
.
1
clock.
The resolution of the CRS signal is 2 ms. The incoming
data is sampled repeatedly during each 2-ms period. If
any activity occurs (regardless of length) during any
2-ms period, this activity will be latched. At the start of
the next 2-ms period the
b
IMR device will examine the
latches for each port. For any port for which activity
occurred, the corresponding bit in the CRS output
stream will remain set for the 2-ms period and will be
reset at the end of this period.
DAT
Data
Input/Output/3-State
In non-collision conditions, the active
drive DAT with NRZ data, including regenerated pre-
amble. During collision, when JAM = HIGH, DAT is
used to signal a multiport (DAT = 0) or single-port
(DAT = 1) condition.
b
IMR device will
When ACK is not asserted, DAT is in high impedance.
If REQ and ACK are both asserted, then DAT is an out-
put. If ACK is asserted and REQ not asserted, then
DAT is an input.
This pin needs to be either pulled up or pulled down
through a high-value resistor.
DI+, DI–
Data In
Input
AUI port differential receiver. Signals comply with IEEE
802.3, Section 7.
DO+, DO–
Data Out
Output
AUI port differential driver. Signals comply with IEEE
802.3, Section 7.
DV
DD
Digital Power
Power Pin
These pins supply +5 V to the logic portions of the
chip and the TXP+/–, TXD+/–, and DO+/– line drivers.
DV
SS
Digital Ground
Ground Pin
These pins are the 0 V reference for DV
b
IMR
DD
.
DV
DD
Pin #
DV
SS
Pin #
Function
19
16
TP ports 0 & 1 drivers
28
31
TP ports 2 & 3 drivers
43, 49
35, 37, 46, 51
Core logic and expansion
and control pins
59
56
TP ports 4 & 5 drivers
68
71
TP ports 6 & 7 drivers
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