參數(shù)資料
型號(hào): AM79C985
廠商: Advanced Micro Devices, Inc.
英文描述: enhanced Integrated Multiport Repeater Plus (eIMR+⑩)
中文描述: 強(qiáng)化的綜合多端中繼器加(eIMR⑩)
文件頁(yè)數(shù): 14/48頁(yè)
文件大?。?/td> 260K
代理商: AM79C985
14
Am79C985
P R E L I M I N A R Y
LED Interface
LDA
0-4
, LDB
LED Drivers
Output, Open Drain
LDA
0-4
and LDB
0-4
drive LED Bank A and LED Bank B,
respectively. LDA
0
and LDB
0
indicate the status of the
AUI port; LDA
1-4
and LDB
1-4
indicate the status of the
four TP ports. The port attributes monitored by LDA
0-4
and LDB
0-4
are programmed by three pins, LDC
0-2
.
0-4
LDGA
Global LED Driver, Bank A
Output, Open Drain
LDGA is the Global LED driver for LED Bank A. The
signal represents global CRS or COL conditions. In a
multiple-eIMR+ configuration, LDGA from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank A.
LDGB
Global LED Driver, Bank B
Output, Open Drain
LDGB is the Global LED driver for LED Bank B. The
signal represents global CRS or JAB conditions. In a
multiple eIMR+ configuration, LDGB from each of the
eIMR+ devices can be tied together to drive a single
global LED in Bank B.
LDC
0-2
LED Control
Input
These pins select the attributes that will be displayed
on LDA
0-4
, LDB
0-4
, LDGA, and LDGB. If an LED is pro-
grammed to display two attributes, the attribute associ-
ated with the periodic blink takes precedence.
ACT
0-7
Activity Display
Output, Open Drain
These signals drive the activity LEDs, which indicate
the percentage of network utilization. The display is up-
dated every 250 ms.
Miscellaneous Pins
RST
Reset
Input, Active LOW
When RST is LOW, the eIMR+ device resets to its de-
fault state. On the rising (trailing) edge of RST, the
eIMR+ also monitors the state of the SELI
0-1
, SI, and
AMODE pins, to configure the operating mode of the
device. In multiple eIMR+ systems, the falling (leading)
edge of the RST signal must be synchronized to CLK.
CLK
Master Clock In
Input
This pin is a 20-MHz clock input.
REXT
External Reference
Input
This pin is used for an internal current reference. It must
be tied to VDD via a 13-k
resistor with 1% tolerance.
VDD
Power
Power Pin
This pin supplies power to the device.
AVSS
Analog Ground
Ground Pin
This pin is the ground reference for the differential
receivers and drivers.
DVSS
Digital Ground
Ground Pin
This pin is the ground reference for all the digital logic
in the eIMR+ device.
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