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參數(shù)資料
| 型號： | AM79C987JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Hardware Implemented Management Information Base (HIMIB) Device |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 183K |
| 代理商： | AM79C987JC |
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AMD
P R E L I M I N A R Y
10
Am79C987
For P = 0 (Repeater Registers), the following registers
are accessible:
R[4:0]
10
12
13
16
28
30
31
Register
Source Address Match (6-byte)
Total Octets (4-byte)
Transmit Collisions (4-byte)
Configuration Register
Version/Device ID
IMR+ Management Port Set Register
IMR+ Management Port Get Register
Register 12 and 13 are 4 bytes long and their contents
are read in the least to most significant byte order.
Register 10 is 6 bytes long and can be read as well as
written to in the least to most significant byte order.
Port Status Registers are organized as follows (P = 1):
R[4:0]
0
1
2
3
4
5
6
7
8
9
Register
TP (Twisted Pair) Ports Partition Status Change
AUI Port Partition Status Change
TP Link Status Change
AUI Loop Back Error
Reserved
AUI SQE Test Error
TP Source Address Change
AUI Source Address Change
TP Source Address Match Status
AUI Source Address Match Status
Port Control Registers are organized as follows (P = 2):
R[4:0]
0
1
2
3
4
5
6
7
Register
TP Partition Change Interrupt Enable
AUI Partition Change Interrupt Enable
TP Link Status Change Interrupt Enable
AUI Loop Back Error Interrupt Enable
Reserved
AUI SQE Test Error Interrupt Enable
TP Source Address Change Interrupt Enable
AUI Source Address Change Interrupt Enable
For other valid port numbers (P in the range 16...23 or
31), the following Attribute Registers are available:
R[4:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Register
Readable Frames
Readable Octets
Frame Check Sequence Errors
Alignment Errors
Frames Too Long
Short Events
Runts
Collisions
Late Events
Very Long Events
Data Rate Mismatches
Auto Partitions
Source Address Changes
Reserved
Last Source Address
Registers 0 through 12 are 4 bytes long and their con-
tents are read in the least to most significant byte order.
Register 14 is 6 bytes long and can be read as well as
written to in the least to most significant byte order.
Note that the contents of all attribute registers are main-
tained during an external reset. At power up, the values
of all 4- and 6-byte attributes are random.
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C987JCB | Hardware Implemented Management Information Base (HIMIB) Device |
| AM79C988A | IC,Motor Controller,CMOS,SOP,8PIN |
| AM79C988 | Quad Integrated Ethernet Transceiver (QuIET⑩) |
| Am79C988BJC | Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C989 | Motor Driver IC; Supply Voltage Max:13.2V; Output Current Max:0.5A; Package/Case:8-SOIC; Driver Type:Motor; Leaded Process Compatible:No; Output Current:1.5A; Peak Reflow Compatible (260 C):No; Supply Voltage Min:3.8V |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C987JCB | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Hardware Implemented Management Information Base (HIMIB) Device |
| AM79C988 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C988A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C988BJC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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