- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C987JCB (ADVANCED MICRO DEVICES INC) Hardware Implemented Management Information Base (HIMIB) Device PDF資料下載
參數(shù)資料
| 型號： | AM79C987JCB |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Hardware Implemented Management Information Base (HIMIB) Device |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大小： | 183K |
| 代理商： | AM79C987JCB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
AMD
P R E L I M I N A R Y
16
Am79C987
TP Link State Change Interrupt Enable
P[4:0] = 2, R[4:0] = 2
Setting any of the bits in this register causes the
INT
pin
to be driven when there is a change in the Link Test
State of the corresponding TP port. The corresponding
status bit in the TP Link Status Change register is set
to1.
D Port Read/Write
MSB
LSB
T6
T7
T5
T4
T3
T2
T1
T0
AUI Loop Back Error Interrupt Enable
P[4:0] = 2, R[4:0] = 3
Setting the A bit to 1 in this register causes the
INT
pin to
be driven when the IMR+ chip senses a Loop Back Error
condition at the AUI port.
D Port Read/Write
MSB
LSB
X
A
X
X
X
X
X
X
Note that the HIMIB device will continue generating in-
terrupts every time a packet is transmitted by the AUI
port while this condition exists. This does not necessar-
ily indicate a problem as an unconnected AUI port will
always report Loop Back Error.
AUI SQE Test Error Interrupt Enable
P[4:0] = 2, R[4:0] = 5
Setting the A bit to 1 in this register causes the
INT
pin to
be driven when the IMR+ chip senses a SQE Test Error
condition at the AUI port (attached MAU has SQE Test
enabled).
Note that the HIMIB device will continue generating in-
terrupts every time a packet is transmitted by the AUI
port, while this condition exists and this interrupt is
enabled.
D Port Read/Write
MSB
LSB
X
A
X
X
X
X
X
X
TP and AUI Source Address Change Interrupt
Enable
These two registers are used to enable or mask inter-
rupts caused by a change in the Source Address of a
port. A TP port connected to another repeater or an AUI
connected to a mixing (multiple DTEs) segment will
have frequent source address changes.
A TP port connected to a single end station will only de-
tect a change of address if the end station is physically
changed to a different MAC address. The Last Source
Address (LSA) register (in the Port Attribute Registers)
of a port known to be connected to a single station can
be programmed with the Node ID (48-bit MAC address)
of the DTE. If the LSA is not programmed after power up
it will be overwritten by the source address of the first
packet received, and generate an interrupt if enabled.
TP Ports
P[4:0] = 2, R[4:0] = 6
D Port Read/Write
MSB
LSB
T6
T7
T5
T4
T3
T2
T1
T0
AUI Port
P[4:0] = 2, R[4:0] = 7
D Port Read/Write
MSB
LSB
X
A
X
X
X
X
X
X
The AUI port only uses the most significant bit (A) and all
other bits are reserved. Software should be designed to
write 0s into unused bits.
Port Attribute Registers
The Port Attribute Registers are accessed in the same
fashion as the Repeater, Status or Control Registers by
writing the appropriate Port Number and Register Num-
ber into the C Port. TP port number zero is accessed by
writing 0001 0000, TP port number one by writing
00010001 and so on. The AUI port attributes are ac-
cessed by writing 00011111 to the CPort.
Except for the Last Source Address (LSA) register, all
other registers are 4 bytes and read only. The (LSA) reg-
ister is 6 bytes long and its contents can be written and
read.
Once the C Port is programmed with a valid Port (Bank)
and Register (Attribute) Number, the corresponding at-
tribute is transferred to a holding register upon reading
the first byte. Subsequent accesses to the D Port read
the value in a least significant to most significant byte or-
der. When reading, once the last byte is read, the attrib-
ute value is re-transferred to the holding register and the
sequence can be restarted. When writing the LSA regis-
ter, if the sequence is aborted prior to the sixth consecu-
tive write cycle, the internally stored register value is not
updated. The sequence (read or write) may be aborted
and restarted by programming the C Port.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C988A | IC,Motor Controller,CMOS,SOP,8PIN |
| AM79C988 | Quad Integrated Ethernet Transceiver (QuIET⑩) |
| Am79C988BJC | Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C989 | Motor Driver IC; Supply Voltage Max:13.2V; Output Current Max:0.5A; Package/Case:8-SOIC; Driver Type:Motor; Leaded Process Compatible:No; Output Current:1.5A; Peak Reflow Compatible (260 C):No; Supply Voltage Min:3.8V |
| AM79C989JC | Quad Ethernet Switching Transceiver (QuEST⑩) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C988 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C988A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Integrated Ethernet Transceiver (QuIET⑩) |
| AM79C988BJC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C988BJC/T | 制造商:Advanced Micro Devices 功能描述:LAN Transceiver, Quad, 44 Pin, Plastic, PLCC 制造商:Advanced Microelectronic Products Inc 功能描述:LAN Transceiver, Quad, 44 Pin, Plastic, PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。