參數(shù)資料
型號: AM79M535
廠商: Advanced Micro Devices, Inc.
英文描述: Metering Subscriber Line Interface Circuit
中文描述: 計量用戶線接口電路
文件頁數(shù): 11/18頁
文件大小: 172K
代理商: AM79M535
SLIC Products
11
Notes:
1. Unless otherwise noted, test conditions are BAT =
48 V, V
CC
= +5 V, V
EE
=
5 V, R
L
= 600
, C
HP
= 0.22
μ
F,
R
DC1
= R
DC2
= 31.25 k
, C
DC
= 0.1
μ
F, R
d
= 51.1 k
, no fuse resistors, two-wire AC output impedance, programming
impedance (Z
T
)= 306 k
resistive, receive input summing impedance (Z
RX
) = 300 k
resistive. (See Table 2 for compo-
nent formulas.)
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at V
TX
by V
RX
. This specification assumes that the two-wire AC load impedance
matches the impedance programmed by Z
T
.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. These tests are performed with a longitudinal impedance of 90
and metallic impedance of 300
for frequencies below
12 kHz and 135
for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.
6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system
design. The Anti-sat 2 region occurs at high loop resistances when
V
BAT
V
AX
V
BX
is less than approximately 17 V.
8.
Midpoint
is defined as the connection point between two 300
series resistors connected between A(TIP) and B(RING).
9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.
10. Total harmonic distortion with metering as specified with a metering signal of 2.2 Vrms at the two-wire output, and a transmit
signal of +3 dBm or receive signal of
4 dBm. The transmit or receive signals are single-frequency inputs, and the distortion
is measured as the highest in-band harmonic at the two-wire or the four-wire output relative to the input signal.
11. Noise with metering is measured by applying a 2.2 Vrms metering signal (measured at the two-wire output) and measuring
the psophometric noise at the two-wire and four-wire outputs over a 200 ms time interval.
12. Tested with 0
source impedance. 2 M
is specified for system design purposes only.
13. Assumes the following Z
T
network:
14. Group delay can be considerably reduced by using a Z
T
network such as that shown in Note 13 above. The network reduces
the group delay to less than 2
μ
s. The effect of group delay on linecard performance may be compensated for by using the
QSLAC
or DSLAC
devices.
Note:
* A logic Low on E0 disables the DET output into the open-collector state.
Table 1.
SLIC Decoding
DET Output
E0 = 1*
E1 = 0
Ring trip
Ring trip
Loop detector
Loop detector
Loop detector
Loop detector
Loop detector
Loop detector
State
C3 C2 C1
Two-Wire Status
E0 = 1*
E1 = 1
Ring trip
Ring trip
Ground key
Ground key
Ground key
Ground key
0
1
2
3
4
5
6
7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Open Circuit
Ringing
Active
On-hook TX (OHT)
Tip Open
Reserved
Active Polarity Reversal
OHT Polarity Reversal
VTX
RSN
153 k
153 k
56 pF
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