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參數(shù)資料
| 型號(hào)： | AM93LC86S |
| 英文描述： | 16384-bits Serial Electrically Erasable PROM |
| 中文描述： | 16384位串行電可擦除可編程ROM |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | AM93LC86S |
AM93LC86
16384-bits Serial Electrically Erasable PROM
(Preliminary)
Anachip Corp.
www.anachip.com.tw
Rev 0.1 Oct 20, 2003
3/12
DC Electrical Characteristics (Vcc =2.7~5.5V, T
A = 25
oC, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Max
Unit
I
CC
Operating current**
CS=VIH, SK=1MHz CMOS input levels
3
mA
I
SB
Standby current
CS=DI=SK=0V
10
A
I
IL
Input leakage
VIN = 0V to VCC(CS,SK,DI)
-1
1
A
I
OL
Output leakage
VOUT = 0V to VCC, CS=0V
-1
1
A
VCC = 3V + 10%
-0.1
0.15 VCC
V
IL
Input low voltage**
VCC = 5V + 10%
-0.1
0.8
V
VCC = 3V + 10%
0.8 VCC
VCC +0.2
V
IH
Input high voltage**
VCC = 5V + 10%
2
VCC+0.2
V
OL1
Output low voltage
IOL = 2.1mA TTL, VCC=5V + 10%
0.4
V
OH1
Output high voltage
IOH = -400uA TTL, VCC=5V + 10%
2.4
V
OL2
Output low voltage
IOL = 10uA CMOS
0.2
V
OL2
Output high voltage
IOH = -10uA CMOS
VCC -0.2
V
Note ** : ICC, VIL min and VIH max are for reference only and are not tested.
AC Electrical Characteristics (Vcc = 2.7V ~ 5.5V, T
A = 25
oC, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Max
Unit
FSK
SK Clock Frequency
0
1
Mhz
TSKH
SK High Time
250
nS
TSKL
SK Low Time
250
nS
TCS
Minimum CS Low Time
250
nS
TCSS
CS Setup Time
Relative to SK
50
nS
TDIS
DI Setup Time
Relative to SK
100
nS
TCSH
CS Hold Time
Relative to SK
0
nS
TDIH
DI Hold Time
Relative to SK
100
nS
TPD1
Output Delay to "1"
AC test (Fig. 1)
500
nS
TPD0
Output Delay to "0"
AC test (Fig. 1)
500
nS
TSV
CS to Status Valid
AC test CL = 100pF
500
nS
TDF
CS to DO in 3-state
CS = VIL
100
nS
TWP
Write Cycle Time
10
mS
Endurance(note)
5V, 25C
1M
write cycles
Note: The parameter is characterized and isn’t 100% tested.
632 ohm
DO
1.247V
(1 TTL Gate Load)
100PF
Figure 1. AC test circuit
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