參數(shù)資料
型號: AMC1210IRHAR
英文描述: Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
中文描述: 四數(shù)字濾波器2階Δ-Σ調(diào)制器
文件頁數(shù): 10/47頁
文件大?。?/td> 805K
代理商: AMC1210IRHAR
www.ti.com
PARALLEL MODE 3
TIMING CHARACTERISTICS
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, BVDD = +2.7V, unless otherwise noted.
ADDR
ADDR
ADDR+1
MSB
LSB
MSB
t
w5
t
d5
t
su1
t
h1
t
su2
t
h2
t
d1
t
d2
t
d3
t
d4
t
w4
t
w3
t
w1
t
w2
AD(7:0)
Internal address
Parallel mode 3, write access
CS
RD
WR
ALE
ADDR
ADDR
ADDR+1
MSB
LSB
MSB
t
d8
t
d6
t
d7
AD(7:0)
Internal address
Parallel mode 3, read access
CS
RD
WR
ALE
AMC1210
SBAS372A–APRIL 2006–REVISED OCTOBER 2006
PARAMETER
(2)
MIN
MAX
UNIT
t
w1
t
w2
t
d1
t
d2
t
d3
t
d4
t
w3
t
w4
t
w5
t
d5
t
su1
t
h1
t
su2
t
h2
t
d6
t
d7
t
d8
CS low width
40
ns
CS high width
5
ns
Delay time from WR low to CS low
5
ns
Delay time from ALE high to CS high
5
ns
Delay time from RD high to CS high
5
ns
Delay time from CS low to RD low
3
ns
RD low width
10
ns
RD high width
30
ns
ALE low width
6
ns
Delay time from ALE high to RD low
10
ns
Setup time from address valid to ALE high
5
ns
Hold time from ALE high to address invalid
5
ns
Setup time from data valid to RD high
5
ns
Hold time from RD high to data invalid
5
ns
Delay time from RD low to data valid
30
ns
Delay time from RD high to databus in tristate
0
10
ns
Delay time from WR high to CS low
5
ns
(1)
(2)
All input signals are specified with t
= t
= 5ns (10% to 90% of BVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
t
w2
is obsolete if CS stays low between the RD and ALE pulses.
Figure 6. Parallel Mode 3 Timing
10
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