參數(shù)資料
型號: AMD-640
英文描述: AMD-640 Chipset IBIS I/O Model Application Note
中文描述: AMD的640芯片組的IBIS I / O模型應(yīng)用筆記
文件頁數(shù): 6/12頁
文件大?。?/td> 377K
代理商: AMD-640
6
AMD-640 Chipset I/O Model
21340A/0—April 1997
To ensure the hold time of a signal is met, the following
relationship must be met:
T
validmin
+ T
propmin
- T
skew
- T
jitter
< T
holdmin
Signal Quality
In addition to providing propagation delays, the simulator can
graphically display the input waveform presented at the input
of the driver and the corresponding waveform produced at
point ‘B’ in Figure 1. This display allows a designer to
determine if the signal quality at the destination is acceptable.
In addition to providing graphical data, most simulators
generate numerical data that quantifies various signal quality
characteristics.
The following list shows the signal quality characteristics that
typically concern designers (all measurements are taken at the
destination receiver):
I
Overshoot
—The difference between the maximum value of
the voltage of a rising signal and the nominal I/O V
cc
voltage (See Figure 4). Overshoot can adversely affect the
reliability of the destination receiver. The time during
which a signal remains above the nominal I/O V
cc
voltage is
also a reliability factor.
Undershoot
—The difference between the minimum value of
the voltage of a falling signal and ground (See Figure 5). As
with overshoot, undershoot can adversely affect the
reliability of the destination receiver.
Ringback
—In the case of a rising waveform, the difference
between the nominal I/O V
cc
voltage and the minimum
voltage of a signal after that signal has reached its
maximum value. In the case of a falling waveform, ringback
is the difference between the maximum voltage of a signal
after that signal has reached its minimum value and ground
(See Figures 4 and 5). Excessive ringing can cause the
destination receiver to falsely switch if the signal traverses
the switching threshold of the receiver.
Ring Settling Time
—In the case of a rising waveform, the
time between when a signal crosses one-half of the nominal
V
cc
I/O voltage and when the signal settles within the
specified tolerance of the I/O V
cc
voltage. In the case of a
falling waveform, ring settling time is the time between
when a signal crosses one-half of the nominal I/O V
cc
voltage and when the signal settles within a specific
I
I
I
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