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參數(shù)資料
| 型號： | AMD27C64-255PI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| 中文描述： | 64千比特（8,192 × 8位）的CMOS存儲器 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 88K |
| 代理商： | AMD27C64-255PI |
AMD
2-18
Am27C64
CAPACITANCE
Parameter
Symbol
Test
Conditions
Parameter Description
Typ
Max
Typ
Max
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
8
10
6
10
5
10
pF
C
OUT
Output Capacitance
V
OUT
= 0
11
14
8
12
8
10
pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz.
CDV028
PL 032
PD 028
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 3 and 4)
Parameter
Test
Conditions
JEDEC
Standard Description
-45
-55
-70
-90
-120
-150
-200
-255
Unit
t
AVQV
t
ACC
Address to
Output Delay
CE
=
OE
=
V
IL
Min
Max
–
–
–
–
–
–
–
–
45
55
70
90
120
150
200
250
ns
t
ELQV
t
CE
Chip Enable to
Output Delay
OE
= V
IL
Min
Max
–
–
–
–
–
–
–
–
45
55
70
90
120
150
200
250
ns
t
GLQV
t
OE
Output Enable to
Output Delay
CE
= V
IL
Min
Max
–
–
–
–
–
–
–
–
30
35
40
40
50
50
50
50
ns
t
EHQZ
t
GHQZ
t
DF
Min
Max
–
–
–
–
–
–
–
–
(Note 2)
25
25
25
25
30
30
30
30
ns
t
AXQX
t
OH
Output Hold from
Addresses,
CE
,or
OE
,
whicheveroccurredfirst
Min
Max
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
ns
Parameter
Symbols
Am27C64
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is only sampled and not 100% tested.
3.
Caution:
The Am27C64 must not be removed from (or inserted into) a socket or board when V
PP
or V
CC
is applied.
4. For the -45, -55 and -70:
Output Load: 1 TTL gate and C
L
= 30 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V for inputs and outputs
For all other versions:
Output Load: 1 TTL gate and C
L
= 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
Chip Enable HIGH or
Output Enable HIGH,
whichever comes
first, to Output Float
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