參數(shù)資料
型號(hào): AMIS-30623AAGA
廠商: ON SEMICONDUCTOR
元件分類: 運(yùn)動(dòng)控制電子
英文描述: STEPPER MOTOR CONTROLLER, 0.8 A, PDSO20
封裝: SOIC-20
文件頁數(shù): 19/67頁
文件大小: 2400K
代理商: AMIS-30623AAGA
AMIS-30623 LIN Microstepping Motordriver
Data Sheet
The <StepLoss> signal is used to block successive motions. Also this signal will be cleared after Vbb > UV1, making updates of
TagPos
possible.
The implementation is illustrated in the state diagram below.
Figure 18: State Diagram Autarkic Under-voltage Handling
GotoPos
HardStop
Stopped
ShutDown
HS to Positioner
GetStatus
GetFullStatus
Vbb > UV1
TagPos
ActPos
If UV2SIG = 1 THEN TagPos
ActPos
ELSE copy TagPos
= ActPos
PWM disabled
Motor in HiZ
HS = f (UV2SIG, OVC1, OVC2, CPFail, …)
In Stop mode 1 AMIS-30623 is in the Stopped state. Because Vbb < UV2 it enters the ShutDown state. Once Vbb > UV1 the Stopped
state will be entered again.
In Stop mode 2 AMIS-30623 is in the GotoPos state. Because Vbb < UV2 the UV2SIG is set and the HardStop state is entered. After
the hardstop motion is finished (HS to Positioner) it enters the Stopped state. UV2SIG = 1 so the TagPos is not copied in Actpos, and
the shutdown stated is entered. Once Vbb > UV1 the Stopped state will be entered again and because TagPos = Actpos C623 moves
to GotoPos again. <UV2SIG>, <CPFail> and <Steploss> are cleared when Vbb > UV1 so HardStop is not entered again.
15.2.8. OTP register
OTP Memory Structure
The table below shows how the parameters to be stored in the OTP memory are located.
Table 17: OTP Memory Structure
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
OSC3
OSC2
OSC1
OSC0
IREF3
IREF2
IREF1
IREF0
0x01
EnableLIN
TSD2
TSD1
TSD0
BG3
BG2
BG1
BG0
0x02
AbsThr3
AbsThr2
AbsThr1
AbsThr0
PA3
PA2
PA1
PA0
0x03
Irun3
Irun2
Irun1
Irun0
Ihold3
Ihold2
Ihold1
Ihold0
0x04
Vmax3
Vmax2
Vmax1
Vmax0
Vmin3
Vmin2
Vmin1
Vmin0
0x05
SecPos10
SecPos9
SecPos8
Shaft
Acc3
Acc2
Acc1
Acc0
0x06
SecPos7
SecPos6
SecPos5
SecPos4
SecPos3
SecPos2
Failsafe
SleepEn
0x07
DelThr3
DelThr2
DelThr1
DelThr0
StepMode1
StepMode0
LOCKBT
LOCKBG
Parameters stored at address 0x00 and 0x01 and bit LOCKBT are already programmed in the OTP memory at circuit delivery. They
correspond to the calibration of the circuit and are just documented here as an indication.
Each OPT bit is at ‘0’ when not zapped. Zapping a bit will set it to ‘1’. Thus only bits having to be at ‘1’ must be zapped. Zapping of a bit
already at ‘1’ is disabled. Each OTP byte will be programmed separately (see command SetOTPparam). Once OTP programming is
completed, bit LOCKBG can be zapped, to disable future zapping, otherwise any OTP bit at ‘0’ could still be zapped by using a
command.
26
AMI Semiconductor
– June 2006, Rev 3.0
www.amis.com
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