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參數(shù)資料
| 型號： | AMIS40616AGA |
| 英文描述： | LIN Transceiver with 5V Voltage Regulator |
| 中文描述： | LIN收發(fā)器與5V的電壓調(diào)節(jié)器 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AMIS40616AGA |
AMIS-40616
LIN Transceiver with 5V Voltage Regulator
Data Sheet
6.0
Typical Application
6.1 Application Schematic
The EMC immunity of the master-mode device can be further enhanced by adding a capacitor between the LIN output and ground. The
optimum value of this capacitor is determined by the length and capacitance of the LIN bus, the number and capacitance of slave
devices, the pull-up resistance of all devices (master & slave), and the required time constant of the system, respectively.
V
cc
voltage must be properly stabilized by external capacitors: capacitor of min. 80nF (ESR<10m
) in parallel with a capacitor of min.
8
μ
F (ESR<1
).
KL30
LIN-BUS
KL31
LIN
V
CC
Master Node
1
1
GND
10 uF
AMIS-
40616
Micro
controller
RxD
TxD
EN
STB
GND
2
INH
LIN
WAKE
V
CC
V
BB
1
5
10
8
9
3 4 11
11
12
13
14
VBAT
GND
1
100nF
7
WAKE
LIN
V
CC
Slave Node
2
GND
10 uF
AMIS-
40616
Micro
controller
RxD
TxD
EN
STB
GND
2
LIN
WAKE
V
CC
V
BB
1
5
10
8
9
3 4 11
11
12
13
14
VBAT
GND
100nF
7
WAKE
10 uF 100nF
10 uF 100nF
1
Figure 2: Typical Application Diagram
6.2 Pin Description
6.2.1. Pin Out (top view)
11
12
13
14
1
2
3
4
RxD
TxD
STB
WAKE
LIN
V
BB
V
CC
A
4
PC20060426.1
5
6
7
10
9
8
GND
GND
OTP_ZAP
INH
GND
EN
TEST
Figure 3: Pin Configuration
4
AMI Semiconductor
– January 2007, M-20545-001
www.amis.com
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